From 8f1b980337ef881ac03f6748c63ac1cb7bbdfc1f Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Sun, 5 May 2019 22:29:33 +0200
Subject: [PATCH] Revert "Add DBusCachedPlugin.relaxedMemoryTranslationRegister
 option"

This reverts commit 5f187053584da0ff522ecf68082bdce7bd88c780.
---
 src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 6 +-----
 src/test/scala/vexriscv/TestIndividualFeatures.scala  | 8 +-------
 2 files changed, 2 insertions(+), 12 deletions(-)

diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index 8584a8c..b8f2ba1 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -23,7 +23,6 @@ class DBusCachedPlugin(config : DataCacheConfig,
                        dBusCmdMasterPipe : Boolean = false,
                        dBusCmdSlavePipe : Boolean = false,
                        dBusRspSlavePipe : Boolean = false,
-                       relaxedMemoryTranslationRegister : Boolean = false,
                        csrInfo : Boolean = false)  extends Plugin[VexRiscv] with DBusAccessService {
   import config._
 
@@ -50,7 +49,6 @@ class DBusCachedPlugin(config : DataCacheConfig,
   object MEMORY_LRSC extends Stageable(Bool)
   object MEMORY_AMO extends Stageable(Bool)
   object IS_DBUS_SHARING extends Stageable(Bool())
-  object MEMORY_VIRTUAL_ADDRESS extends Stageable(UInt(32 bits))
 
   override def setup(pipeline: VexRiscv): Unit = {
     import Riscv._
@@ -214,8 +212,6 @@ class DBusCachedPlugin(config : DataCacheConfig,
       when(cache.io.cpu.redo && arbitration.isValid && input(MEMORY_ENABLE)){
         arbitration.haltItself := True
       }
-
-      if(relaxedMemoryTranslationRegister) insert(MEMORY_VIRTUAL_ADDRESS) := cache.io.cpu.execute.address
     }
 
     memory plug new Area{
@@ -223,7 +219,7 @@ class DBusCachedPlugin(config : DataCacheConfig,
       cache.io.cpu.memory.isValid := arbitration.isValid && input(MEMORY_ENABLE)
       cache.io.cpu.memory.isStuck := arbitration.isStuck
       cache.io.cpu.memory.isRemoved := arbitration.removeIt
-      cache.io.cpu.memory.address := (if(relaxedMemoryTranslationRegister) input(MEMORY_VIRTUAL_ADDRESS) else U(input(REGFILE_WRITE_DATA)))
+      cache.io.cpu.memory.address := U(input(REGFILE_WRITE_DATA))
 
       cache.io.cpu.memory.mmuBus <> mmuBus
       cache.io.cpu.memory.mmuBus.rsp.isIoAccess setWhen(pipeline(DEBUG_BYPASS_CACHE) && !cache.io.cpu.memory.isWrite)
diff --git a/src/test/scala/vexriscv/TestIndividualFeatures.scala b/src/test/scala/vexriscv/TestIndividualFeatures.scala
index 03cf8ee..cedf989 100644
--- a/src/test/scala/vexriscv/TestIndividualFeatures.scala
+++ b/src/test/scala/vexriscv/TestIndividualFeatures.scala
@@ -396,13 +396,11 @@ class DBusDimension extends VexRiscvDimension("DBus") {
       var wayCount = 0
       val withLrSc = catchAll
       val withAmo = catchAll && r.nextBoolean()
-      val dBusCmdMasterPipe, dBusCmdSlavePipe, dBusRspSlavePipe, relaxedMemoryTranslationRegister = r.nextBoolean()
-
       do{
         cacheSize = 512 << r.nextInt(5)
         wayCount = 1 << r.nextInt(3)
       }while(cacheSize/wayCount < 512 || (catchAll && cacheSize/wayCount > 4096))
-      new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine + (if(dBusCmdMasterPipe) "Cmp " else "") + (if(dBusCmdSlavePipe) "Csp " else "") + (if(dBusRspSlavePipe) "Rsp " else "") + (if(relaxedMemoryTranslationRegister) "Rmtr " else "")) {
+      new VexRiscvPosition("Cached" + "S" + cacheSize + "W" + wayCount + "BPL" + bytePerLine) {
         override def testParam = "DBUS=CACHED " + (if(withLrSc) "LRSC=yes " else "")  + (if(withAmo) "AMO=yes " else "")
 
         override def applyOn(config: VexRiscvConfig): Unit = {
@@ -420,10 +418,6 @@ class DBusDimension extends VexRiscvDimension("DBus") {
               withLrSc = withLrSc,
               withAmo = withAmo
             ),
-            dBusCmdMasterPipe = dBusCmdMasterPipe,
-            dBusCmdSlavePipe = dBusCmdSlavePipe,
-            dBusRspSlavePipe = dBusRspSlavePipe,
-            relaxedMemoryTranslationRegister = relaxedMemoryTranslationRegister,
             memoryTranslatorPortConfig = mmuConfig
           )
         }