From 8fbd7777943c6fbec2971ebcc56d5bb51083fb07 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Mon, 14 Aug 2017 11:40:33 +0200 Subject: [PATCH] Update readme with GCC changes from the VexRiscvSocSoftware repo --- README.md | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/README.md b/README.md index e9aa1e8..cd64908 100644 --- a/README.md +++ b/README.md @@ -295,7 +295,13 @@ There is some scripts to generate the SoC and call the icestorm toolchain there ## Build the RISC-V GCC -To install in /opt/ the rv32i and rv32im gcc, do the following (will take hours): +In fact, you can find some prebuild GCC :
+- https://www.sifive.com/products/tools/ => SiFive GNU Embedded Toolchain + +The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/rv/__contentOfThisPreBuild__ + + +But if you want to compile from sources in /opt/ the rv32i and rv32im gcc, do the following (will take hours): ```sh # Be carefull, sometime the git clone has issue to successfully clone riscv-gnu-toolchain.