From 8fc5f35d299bc323a12ac3c5419e4a50b916b2c0 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Mon, 24 Apr 2023 13:13:55 +0200
Subject: [PATCH] DBusCachedPlugin now provide writesPending signal

---
 src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index 623add8..bcdad63 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -64,6 +64,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
   var exceptionBus : Flow[ExceptionCause] = null
   var privilegeService : PrivilegeService = null
   var redoBranch : Flow[UInt] = null
+  var writesPending : Bool = null
 
   @dontName var dBusAccess : DBusAccess = null
   override def newDBusAccess(): DBusAccess = {
@@ -270,6 +271,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
         decoderService.add(FENCE, List(MEMORY_FENCE -> True))
         decoderService.addDefault(MEMORY_FENCE_WR, False)
         decoderService.add(FENCE_I, List(MEMORY_FENCE_WR -> True))
+        writesPending = Bool().setCompositeName(this, "writesPending")
       }
     }
 
@@ -412,6 +414,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
         when(arbitration.isValid && input(MEMORY_FENCE_WR) && cache.io.cpu.writesPending){
           arbitration.haltItself := True
         }
+        writesPending := cache.io.cpu.writesPending
       }
 
       if(tightlyGen){