From 915db9d6c96647f9a0cc4c4510053554a27c08a7 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 18 Mar 2019 20:50:19 +0100 Subject: [PATCH] cleaning --- src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index a5a91ae..701bbfb 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -290,12 +290,10 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, val cmdSent = if(rspStage == execute) RegInit(False) setWhen(dBus.cmd.fire) clearWhen(!execute.arbitration.isStuck) else False - insert(ALIGNEMENT_FAULT) := { - if (catchAddressMisaligned) - (dBus.cmd.size === 2 && dBus.cmd.address(1 downto 0) =/= 0) || (dBus.cmd.size === 1 && dBus.cmd.address(0 downto 0) =/= 0) - else - False - } + if (catchAddressMisaligned) + insert(ALIGNEMENT_FAULT) := (dBus.cmd.size === 2 && dBus.cmd.address(1 downto 0) =/= 0) || (dBus.cmd.size === 1 && dBus.cmd.address(0 downto 0) =/= 0) + else + insert(ALIGNEMENT_FAULT) := False val skipCmd = False @@ -321,6 +319,7 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false, U(1) -> B"0011", default -> B"1111" ) |<< dBus.cmd.address(1 downto 0) + insert(FORMAL_MEM_ADDR) := dBus.cmd.address & U"xFFFFFFFC" insert(FORMAL_MEM_WMASK) := (dBus.cmd.valid && dBus.cmd.wr) ? formalMask | B"0000" insert(FORMAL_MEM_RMASK) := (dBus.cmd.valid && !dBus.cmd.wr) ? formalMask | B"0000"