diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
index 941874f..a43e55f 100644
--- a/src/main/scala/vexriscv/ip/DataCache.scala
+++ b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -133,11 +133,13 @@ case class DataCacheCpuBus(p : DataCacheConfig) extends Bundle with IMasterSlave
   val writeBack = DataCacheCpuWriteBack(p)
 
   val redo = Bool()
+  val flush = Event
 
   override def asMaster(): Unit = {
     master(execute)
     master(memory)
     master(writeBack)
+    master(flush)
     in(redo)
   }
 }
@@ -298,7 +300,6 @@ case class DataCacheMemBus(p : DataCacheConfig) extends Bundle with IMasterSlave
 
 class DataCache(p : DataCacheConfig) extends Component{
   import p._
-  assert(wayCount == 1)
   assert(cpuDataWidth == memDataWidth)
 
   val io = new Bundle{
@@ -449,13 +450,20 @@ class DataCache(p : DataCacheConfig) extends Component{
         tagsWriteCmd.address := mmuRsp.physicalAddress(lineRange)
         tagsWriteCmd.way.setAll()
         tagsWriteCmd.data.valid := False
-        when(mmuRsp.physicalAddress(lineRange) =/= lineCount - 1) {
+        when(mmuRsp.physicalAddress(lineRange) =/= wayLineCount - 1) {
           mmuRsp.physicalAddress.getDrivingReg(lineRange) := mmuRsp.physicalAddress(lineRange) + 1
           io.cpu.writeBack.haltIt := True
         } otherwise {
           valid := False
         }
       }
+
+      io.cpu.flush.ready := False
+      when(io.cpu.flush.valid && !io.cpu.execute.isValid && !io.cpu.memory.isValid && !io.cpu.writeBack.isValid && !io.cpu.redo){
+        io.cpu.flush.ready := True
+        mmuRsp.physicalAddress.getDrivingReg(lineRange) := 0
+        valid := True
+      }
     }
 
 
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index 3793ae4..e7bde27 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -61,15 +61,13 @@ class DBusCachedPlugin(config : DataCacheConfig,
       REGFILE_WRITE_VALID -> True,
       BYPASSABLE_EXECUTE_STAGE -> False,
       BYPASSABLE_MEMORY_STAGE -> False,
-      MEMORY_WR -> False,
-      MEMORY_MANAGMENT -> False
+      MEMORY_WR -> False
     ) ++ (if(catchSomething) List(HAS_SIDE_EFFECT -> True) else Nil)
 
     val storeActions = stdActions ++ List(
       SRC2_CTRL -> Src2CtrlEnum.IMS,
       RS2_USE -> True,
-      MEMORY_WR -> True,
-      MEMORY_MANAGMENT -> False
+      MEMORY_WR -> True
     )
 
     decoderService.addDefault(MEMORY_ENABLE, False)
@@ -102,9 +100,9 @@ class DBusCachedPlugin(config : DataCacheConfig,
     }
 
     def MANAGEMENT  = M"-------00000-----101-----0001111"
-    decoderService.add(MANAGEMENT, stdActions ++ List(
-      SRC2_CTRL -> Src2CtrlEnum.RS,
-      RS2_USE -> True,
+
+    decoderService.addDefault(MEMORY_MANAGMENT, False)
+    decoderService.add(MANAGEMENT, List(
       MEMORY_MANAGMENT -> True
     ))
 
@@ -161,6 +159,10 @@ class DBusCachedPlugin(config : DataCacheConfig,
       )
       cache.io.cpu.execute.args.size := size
       cache.io.cpu.execute.args.forceUncachedAccess := False
+
+      cache.io.cpu.flush.valid := arbitration.isValid && input(MEMORY_MANAGMENT)
+      arbitration.haltItself setWhen(cache.io.cpu.flush.isStall)
+
       if(genAtomic) {
         cache.io.cpu.execute.args.isAtomic := False
         when(input(MEMORY_ATOMIC)){