From 930563291c4ed1806ee8c16e10c32f3633019ff8 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 5 Jun 2018 02:21:05 +0200 Subject: [PATCH] Allow RVC/dynamic_target/fetch bus latency > 1 all together Fix freeretos rvc regressions --- src/main/scala/vexriscv/TestsWorkspace.scala | 5 +-- src/main/scala/vexriscv/plugin/Fetcher.scala | 38 ++++++++++++-------- src/test/cpp/regression/main.cpp | 13 ++++--- 3 files changed, 35 insertions(+), 21 deletions(-) diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index e65b441..22e3c89 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -35,9 +35,10 @@ object TestsWorkspace { resetVector = 0x80000000l, relaxedPcCalculation = false, prediction = DYNAMIC_TARGET, - historyRamSizeLog2 = 12, + historyRamSizeLog2 = 10, catchAccessFault = true, - compressedGen = true + compressedGen = true, + busLatencyMin = 3 ), // new IBusCachedPlugin( // resetVector = 0x80000000l, diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 39c83cd..ac7b6df 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -22,6 +22,7 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, var prefetchExceptionPort : Flow[ExceptionCause] = null var decodePrediction : DecodePredictionBus = null var fetchPrediction : FetchPredictionBus = null + var dynamicTargetFailureCorrection : Flow[UInt] = null var externalResetVector : UInt = null assert(cmdToRspStageCount >= 1) assert(!(cmdToRspStageCount == 1 && !injectorStage)) @@ -71,6 +72,9 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, } case DYNAMIC_TARGET => { fetchPrediction = pipeline.service(classOf[PredictionInterface]).askFetchPrediction() + if(compressedGen && cmdToRspStageCount > 1){ + dynamicTargetFailureCorrection = createJumpInterface(pipeline.decode) + } } } } @@ -304,10 +308,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, else if (cmdToRspStageCount > 1) iBusRsp.inputPipeline(cmdToRspStageCount - 2) else throw new Exception("Fetch should at least have two stages") - // when(fetcherHalt){ - // lastStageStream.valid := False - // lastStageStream.ready := False - // } decodeNextPcValid := RegNext(lastStageStream.isStall) decodeNextPc := decode.input(PC) } @@ -319,12 +319,6 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, decode.insert(INSTRUCTION_READY) := True if (compressedGen) decode.insert(IS_RVC) := decodeInput.isRvc - // if(catchAccessFault){ - // decodeExceptionPort.valid := decode.arbitration.isValid && decodeInput.rsp.error - // decodeExceptionPort.code := 1 - // decodeExceptionPort.badAddr := decode.input(PC) - // } - if (injectionPort != null) { Component.current.addPrePopTask(() => { val state = RegInit(U"000") @@ -480,9 +474,8 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, // } } case DYNAMIC_TARGET => new Area{ - assert(!compressedGen || cmdToRspStageCount == 1, "Can't combine DYNAMIC_TARGET and RVC as it could stop the instruction fetch mid-air") +// assert(!compressedGen || cmdToRspStageCount == 1, "Can't combine DYNAMIC_TARGET and RVC as it could stop the instruction fetch mid-air") - val historyRamSizeLog2 : Int = 10 case class BranchPredictorLine() extends Bundle{ val source = Bits(30 - historyRamSizeLog2 bits) val branchWish = UInt(2 bits) @@ -567,8 +560,25 @@ abstract class IBusFetcherImpl(val catchAccessFault : Boolean, - ifGen(compressedGen)({ - // val decompressionFalure = decompressor.output. + val predictionFailure = ifGen(compressedGen && cmdToRspStageCount > 1)(new Area{ + val decompressorFailure = RegInit(False) + when(decompressor.input.fire){ + decompressorFailure := decompressorContext.hit && !decompressorContext.hazard && !decompressor.output.valid && decompressorContext.line.branchWish(1) + } + decompressorFailure clearWhen(flush || decompressor.output.fire) + + val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready) + + dynamicTargetFailureCorrection.valid := False + dynamicTargetFailureCorrection.payload := decode.input(PC) + when(injector.decodeInput.valid && injectorFailure){ + historyWrite.valid := True + historyWrite.address := (decode.input(PC) >> 2).resized + historyWrite.data.branchWish := 0 + + decode.arbitration.isValid := False + dynamicTargetFailureCorrection.valid := True + } }) } } diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 561d8b0..f0fd4d7 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -1913,13 +1913,16 @@ int main(int argc, char **argv, char **env) { for(const string &name : freeRtosTests){ tasks.push([=]() { Workspace(name + "_rv32i_O0").loadHex("../../resources/freertos/" + name + "_rv32i_O0.hex")->bootAt(0x80000000u)->run(4e6*15);}); tasks.push([=]() { Workspace(name + "_rv32i_O3").loadHex("../../resources/freertos/" + name + "_rv32i_O3.hex")->bootAt(0x80000000u)->run(4e6*15);}); - #ifndef COMPRESSED - tasks.push([=]() { Workspace(name + "_rv32ic_O0").loadHex("../../resources/freertos/" + name + "_rv32i_O0.hex")->bootAt(0x80000000u)->run(4e6*15);}); - tasks.push([=]() { Workspace(name + "_rv32ic_O3").loadHex("../../resources/freertos/" + name + "_rv32i_O3.hex")->bootAt(0x80000000u)->run(4e6*15);}); + #ifdef COMPRESSED + tasks.push([=]() { Workspace(name + "_rv32ic_O0").loadHex("../../resources/freertos/" + name + "_rv32ic_O0.hex")->bootAt(0x80000000u)->run(4e6*15);}); + tasks.push([=]() { Workspace(name + "_rv32ic_O3").loadHex("../../resources/freertos/" + name + "_rv32ic_O3.hex")->bootAt(0x80000000u)->run(4e6*15);}); #endif #if defined(MUL) && defined(DIV) - //tasks.push([=]() { Workspace(name + "_rv32im_O0").loadHex("../../resources/freertos/" + name + "_rv32im_O0.hex")->bootAt(0x80000000u)->run(4e6*15);}); - tasks.push([=]() { Workspace(name + "_rv32imac_O3").loadHex("../../resources/freertos/" + name + "_rv32im_O3.hex")->bootAt(0x80000000u)->run(4e6*15);}); + #ifdef COMPRESSED + tasks.push([=]() { Workspace(name + "_rv32imac_O3").loadHex("../../resources/freertos/" + name + "_rv32imac_O3.hex")->bootAt(0x80000000u)->run(4e6*15);}); + #else + tasks.push([=]() { Workspace(name + "_rv32im_O3").loadHex("../../resources/freertos/" + name + "_rv32im_O3.hex")->bootAt(0x80000000u)->run(4e6*15);}); + #endif #endif }