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VexRiscv
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fix #376 Uncached dbus ahb, add option to ensure no combinatorial loop

This commit is contained in:
Dolu1990 2023-11-14 11:35:56 +01:00
parent 1849aa4419
commit 940fb507a5
1 changed files with 11 additions and 10 deletions
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21
src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
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@ -225,29 +225,30 @@ case class DBusSimpleBus(bigEndian : Boolean = false) extends Bundle with IMaste
bus bus
} }
def toAhbLite3Master(avoidWriteToReadHazard : Boolean): AhbLite3Master = { def toAhbLite3Master(avoidWriteToReadHazard : Boolean, withHalfRate : Boolean = true): AhbLite3Master = {
val bus = AhbLite3Master(DBusSimpleBus.getAhbLite3Config()) val bus = AhbLite3Master(DBusSimpleBus.getAhbLite3Config())
bus.HADDR := this.cmd.address val cmdBuffer = this.cmd.pipelined(halfRate = withHalfRate)
bus.HWRITE := this.cmd.wr bus.HADDR := cmdBuffer.address
bus.HSIZE := B(this.cmd.size, 3 bits) bus.HWRITE := cmdBuffer.wr
bus.HSIZE := B(cmdBuffer.size, 3 bits)
bus.HBURST := 0 bus.HBURST := 0
bus.HPROT := "1111" bus.HPROT := "1111"
bus.HTRANS := this.cmd.valid ## B"0" bus.HTRANS := cmdBuffer.valid ## B"0"
bus.HMASTLOCK := False bus.HMASTLOCK := False
bus.HWDATA := RegNextWhen(this.cmd.data, bus.HREADY) bus.HWDATA := RegNextWhen(cmdBuffer.data, bus.HREADY)
this.cmd.ready := bus.HREADY cmdBuffer.ready := bus.HREADY
val pending = RegInit(False) clearWhen(bus.HREADY) setWhen(this.cmd.fire && !this.cmd.wr) val pending = RegInit(False) clearWhen(bus.HREADY) setWhen(cmdBuffer.fire && !cmdBuffer.wr)
this.rsp.ready := bus.HREADY && pending this.rsp.ready := bus.HREADY && pending
this.rsp.data := bus.HRDATA this.rsp.data := bus.HRDATA
this.rsp.error := bus.HRESP this.rsp.error := bus.HRESP
if(avoidWriteToReadHazard) { if(avoidWriteToReadHazard) {
val writeDataPhase = RegNextWhen(bus.HTRANS === 2 && bus.HWRITE, bus.HREADY) init (False) val writeDataPhase = RegNextWhen(bus.HTRANS === 2 && bus.HWRITE, bus.HREADY) init (False)
val potentialHazard = this.cmd.valid && !this.cmd.wr && writeDataPhase val potentialHazard = cmdBuffer.valid && !cmdBuffer.wr && writeDataPhase
when(potentialHazard) { when(potentialHazard) {
bus.HTRANS := 0 bus.HTRANS := 0
this.cmd.ready := False cmdBuffer.ready := False
} }
} }
bus bus