From 9462496386b193abc94b505cf8d49ef59aba9124 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Thu, 25 Mar 2021 14:14:19 +0100
Subject: [PATCH] Add rvc support and fix rvc with FPU

---
 .../scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala   | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
index 8af6bf1..4f0936e 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
@@ -115,6 +115,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
   var aesInstruction = false
   var fpu = false
   var cpuPerFpu = 4
+  var rvc = false
   var netlistDirectory = "."
   var netlistName = "VexRiscvLitexSmpCluster"
   assert(new scopt.OptionParser[Unit]("VexRiscvLitexSmpClusterCmdGen") {
@@ -135,6 +136,7 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
     opt[String]("wishbone-memory" ) action { (v, c) => wishboneMemory = v.toBoolean  }
     opt[String]("fpu" ) action { (v, c) => fpu = v.toBoolean  }
     opt[String]("cpu-per-fpu") action { (v, c) => cpuPerFpu = v.toInt }
+    opt[String]("rvc") action { (v, c) => rvc = v.toBoolean }
   }.parse(args))
 
   val coherency = coherentDma || cpuCount > 1
@@ -157,7 +159,9 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
           withFloat = fpu,
           withDouble = fpu,
           externalFpu = fpu,
-          loadStoreWidth = if(fpu) 64 else 32
+          loadStoreWidth = if(fpu) 64 else 32,
+          rvc = rvc,
+          injectorStage = rvc
         )
         if(aesInstruction) c.add(new AesPlugin)
         c