From b86047901ae55a3ea0dc892acf1e72c2f0012118 Mon Sep 17 00:00:00 2001 From: buncram Date: Mon, 19 Dec 2022 19:03:33 +0800 Subject: [PATCH 1/4] add flag to expose SATP externally --- .../scala/vexriscv/plugin/MmuPlugin.scala | 20 ++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/MmuPlugin.scala b/src/main/scala/vexriscv/plugin/MmuPlugin.scala index c984b03..73efaf0 100644 --- a/src/main/scala/vexriscv/plugin/MmuPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MmuPlugin.scala @@ -41,7 +41,9 @@ case class MmuPortConfig(portTlbSize : Int, latency : Int = 0, earlyRequireMmuLo class MmuPlugin(ioRange : UInt => Bool, virtualRange : UInt => Bool = address => True, // allowUserIo : Boolean = false, - enableMmuInMachineMode : Boolean = false) extends Plugin[VexRiscv] with MemoryTranslator { + enableMmuInMachineMode : Boolean = false, + exportSatp: Boolean = false + ) extends Plugin[VexRiscv] with MemoryTranslator { var dBusAccess : DBusAccess = null val portsInfo = ArrayBuffer[MmuPort]() @@ -91,10 +93,18 @@ class MmuPlugin(ioRange : UInt => Bool, val sum, mxr, mprv = RegInit(False) mprv clearWhen(csrService.xretAwayFromMachine) } - val satp = new Area { - val mode = RegInit(False) - val asid = Reg(Bits(9 bits)) - val ppn = Reg(UInt(20 bits)) + val satp = if(exportSatp) { + new Area { + val mode = out(RegInit(False)) + val asid = out(Reg(Bits(9 bits))) + val ppn = out(Reg(UInt(20 bits))) + } + } else { + new Area { + val mode = RegInit(False) + val asid = Reg(Bits(9 bits)) + val ppn = Reg(UInt(20 bits)) + } } for(offset <- List(CSR.MSTATUS, CSR.SSTATUS)) csrService.rw(offset, 19 -> status.mxr, 18 -> status.sum, 17 -> status.mprv) From 2297f8aea0133f3304bdc6493bdb157d66fce63d Mon Sep 17 00:00:00 2001 From: buncram Date: Mon, 16 Jan 2023 02:16:25 +0800 Subject: [PATCH 2/4] also need to expose privilege state turns out SATP is not enough to figure out what code you're running, because the kernel code is mapped into all userspace's virtual memory areas. You also need the privilege state to be exported. This creates an option to export those bits. --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 928fe07..c2ab72a 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -82,6 +82,7 @@ case class CsrPluginConfig( deterministicInteruptionEntry : Boolean = false, //Only used for simulatation purposes wfiOutput : Boolean = false, withPrivilegedDebug : Boolean = false, //For the official RISC-V debug spec implementation + exportPrivilege : Boolean = false, var debugTriggers : Int = 2 ){ assert(!ucycleAccess.canWrite) @@ -612,6 +613,9 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep contextSwitching = Bool().setName("contextSwitching") privilege = UInt(2 bits).setName("CsrPlugin_privilege") + if (exportPrivilege) { + val export_priv = out(privilege) + } forceMachineWire = False if(catchIllegalAccess || ecallGen || withEbreak) From ed5babaaab9daac276806c0ca0ba98e5c8c5df62 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 16 Jan 2023 12:39:55 +0100 Subject: [PATCH 3/4] shorter syntax on privilege export --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index c2ab72a..8eeb898 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -613,9 +613,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep contextSwitching = Bool().setName("contextSwitching") privilege = UInt(2 bits).setName("CsrPlugin_privilege") - if (exportPrivilege) { - val export_priv = out(privilege) - } + if (exportPrivilege) out(privilege) forceMachineWire = False if(catchIllegalAccess || ecallGen || withEbreak) From 0aa6e0573d6f69bacbe6006ea801944e19175b88 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 16 Jan 2023 12:43:01 +0100 Subject: [PATCH 4/4] shorter satp export --- src/main/scala/vexriscv/plugin/MmuPlugin.scala | 18 ++++++------------ 1 file changed, 6 insertions(+), 12 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/MmuPlugin.scala b/src/main/scala/vexriscv/plugin/MmuPlugin.scala index 423b1ce..f8bd88f 100644 --- a/src/main/scala/vexriscv/plugin/MmuPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MmuPlugin.scala @@ -93,18 +93,12 @@ class MmuPlugin(ioRange : UInt => Bool, val sum, mxr, mprv = RegInit(False) mprv clearWhen(csrService.xretAwayFromMachine) } - val satp = if(exportSatp) { - new Area { - val mode = out(RegInit(False)) - val asid = out(Reg(Bits(9 bits))) - // Bottom 20 bits are used in implementation, but top 2 bits are still stored for OS use. - val ppn = out(Reg(UInt(22 bits))) - } - } else { - new Area { - val mode = RegInit(False) - val asid = Reg(Bits(9 bits)) - val ppn = Reg(UInt(22 bits)) + val satp = new Area { + val mode = RegInit(False) + val asid = Reg(Bits(9 bits)) + val ppn = Reg(UInt(22 bits)) // Bottom 20 bits are used in implementation, but top 2 bits are still stored for OS use. + if(exportSatp) { + out(mode, asid, ppn) } }