From 950944e0401e72699107a58d16c8b3b1403a5d8a Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Wed, 19 Jul 2017 18:36:30 +0200
Subject: [PATCH] typo fix

---
 README.md | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/README.md b/README.md
index d0b1bf8..31fe933 100644
--- a/README.md
+++ b/README.md
@@ -198,10 +198,13 @@ You can find multiples software examples and demo there : https://github.com/Spi
 You can find some FPGA project which instantiate the Briey SoC there (DE1-SoC, DE0-Nano): https://drive.google.com/drive/folders/0B-CqLXDTaMbKZGdJZlZ5THAxRTQ?usp=sharing
 
 There is some measurements of Briey SoC timings and area : 
+
+```
   Artix 7    -> 230 Mhz 3551 LUT 3612 FF 
   Cyclone V  -> 126 Mhz 2,608 ALMs
   Cyclone IV -> 117 Mhz 5,196 LUT 3,784 FF 
   Cyclone II -> 102 Mhz 5,321 LUT 3,787 FF 
+```
 
 ## Build the RISC-V GCC