From 95c3e436dceea548702a882f0a3c44d05af482a5 Mon Sep 17 00:00:00 2001 From: Tom Verbeure Date: Sat, 23 Mar 2019 22:32:48 +0000 Subject: [PATCH] Make toPipelinedMemoryBus() just like the other busses --- src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 636b193..5d6ad0b 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -59,6 +59,11 @@ object IBusSimpleBus{ useBTE = true, useCTI = true ) + + def getPipelinedMemoryBusConfig() = PipelinedMemoryBusConfig( + addressWidth = 32, + dataWidth = 32 + ) } @@ -136,7 +141,8 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit } def toPipelinedMemoryBus(): PipelinedMemoryBus = { - val bus = PipelinedMemoryBus(32,32) + val pipelinedMemoryBusConfig = IBusSimpleBus.getPipelinedMemoryBusConfig() + val bus = PipelinedMemoryBus(pipelinedMemoryBusConfig) bus.cmd.arbitrationFrom(cmd) bus.cmd.address := cmd.pc.resized bus.cmd.write := False @@ -281,4 +287,4 @@ class IBusSimplePlugin(resetVector : BigInt, } } } -} \ No newline at end of file +}