From 961abb3cf10bab123e62445d7c0ab5d13470eff7 Mon Sep 17 00:00:00 2001 From: Brett Foster Date: Sat, 22 Dec 2018 07:58:59 -0800 Subject: [PATCH] Avalon: Debug Clock Domain for JTAG This change ensures that the clock domain for the JTAG interface uses the debug plugin's domain. Otherwise, resetting the processor will put the jtag debugger in to reset as well. See SpinalHDL/VexRiscv#48 --- .../scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala | 2 +- .../scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala index e4793d2..8908cad 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalonWithIntegratedJtag.scala @@ -162,7 +162,7 @@ object VexRiscvAvalonWithIntegratedJtag{ .setName("dBusAvalon") .addTag(ClockDomainTag(ClockDomain.current)) } - case plugin: DebugPlugin => { + case plugin: DebugPlugin => plugin.debugClockDomain { plugin.io.bus.setAsDirectionLess() val jtag = slave(new Jtag()) .setName("jtag") diff --git a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala index 9f339fb..8947636 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAxi4WithIntegratedJtag.scala @@ -163,7 +163,7 @@ object VexRiscvAxi4WithIntegratedJtag{ .setName("dBusAxi") .addTag(ClockDomainTag(ClockDomain.current)) } - case plugin: DebugPlugin => { + case plugin: DebugPlugin => plugin.debugClockDomain { plugin.io.bus.setAsDirectionLess() val jtag = slave(new Jtag()) .setName("jtag")