diff --git a/README.md b/README.md index 76f511b..d192005 100644 --- a/README.md +++ b/README.md @@ -65,55 +65,54 @@ dhrystone binaries which fit inside a 4KB I$ and 4KB D$ (I already had this case The CPU configurations used below can be found in the `src/scala/vexriscv/demo` directory. ``` -VexRiscv smallest (RV32I, 0.52 DMIPS/Mhz, no datapath bypass, no interrupt) -> - Artix 7 -> 233 Mhz 494 LUT 505 FF - Cyclone V -> 193 Mhz 347 ALMs - Cyclone IV -> 179 Mhz 730 LUT 494 FF +VexRiscv small (RV32I, 0.52 DMIPS/Mhz, no datapath bypass, no interrupt) -> + Artix 7 -> 243 Mhz 504 LUT 505 FF + Cyclone V -> 174 Mhz 352 ALMs + Cyclone IV -> 179 Mhz 731 LUT 494 FF iCE40 -> 92 Mhz 1130 LC -VexRiscv smallest (RV32I, 0.52 DMIPS/Mhz, no datapath bypass) -> - Artix 7 -> 232 Mhz 538 LUT 562 FF - Cyclone V -> 189 Mhz 387 ALMs - Cyclone IV -> 175 Mhz 829 LUT 550 FF +VexRiscv small (RV32I, 0.52 DMIPS/Mhz, no datapath bypass) -> + Artix 7 -> 240 Mhz 556 LUT 566 FF + Cyclone V -> 194 Mhz 394 ALMs + Cyclone IV -> 174 Mhz 831 LUT 555 FF iCE40 -> 85 Mhz 1292 LC VexRiscv small and productive (RV32I, 0.82 DMIPS/Mhz) -> - Artix 7 -> 226 Mhz 689 LUT 531 FF - Cyclone V -> 145 Mhz 499 ALMs - Cyclone IV -> 150 Mhz 1,111 LUT 525 FF + Artix 7 -> 232 Mhz 816 LUT 534 FF + Cyclone V -> 155 Mhz 492 ALMs + Cyclone IV -> 155 Mhz 1,111 LUT 530 FF iCE40 -> 63 Mhz 1596 LC VexRiscv small and productive with I$ (RV32I, 0.70 DMIPS/Mhz, 4KB-I$) -> - Artix 7 -> 230 Mhz 734 LUT 564 FF - Cyclone V -> 145 Mhz 511 ALMs - Cyclone IV -> 144 Mhz 1,145 LUT 531 FF + Artix 7 -> 220 Mhz 730 LUT 570 FF + Cyclone V -> 142 Mhz 501 ALMs + Cyclone IV -> 150 Mhz 1,139 LUT 536 FF iCE40 -> 66 Mhz 1680 LC VexRiscv full no cache (RV32IM, 1.21 DMIPS/Mhz 2.30 Coremark/Mhz, single cycle barrel shifter, debug module, catch exceptions, static branch) -> - Artix 7 -> 219 Mhz 1537 LUT 977 FF - Cyclone V -> 139 Mhz 958 ALMs - Cyclone IV -> 135 Mhz 2,011 LUT 968 FF + Artix 7 -> 216 Mhz 1418 LUT 949 FF + Cyclone V -> 133 Mhz 933 ALMs + Cyclone IV -> 143 Mhz 2,076 LUT 972 FF VexRiscv full (RV32IM, 1.21 DMIPS/Mhz 2.30 Coremark/Mhz with cache trashing, 4KB-I$,4KB-D$, single cycle barrel shifter, debug module, catch exceptions, static branch) -> - Artix 7 -> 193 Mhz 1706 LUT 1172 FF - Cyclone V -> 144 Mhz 1,128 ALMs - Cyclone IV -> 133 Mhz 2,298 LUT 1,096 FF + Artix 7 -> 199 Mhz 1840 LUT 1158 FF + Cyclone V -> 141 Mhz 1,166 ALMs + Cyclone IV -> 131 Mhz 2,407 LUT 1,067 FF -VexRiscv full max dmips/mhz -> (RV32IM, 1.44 DMIPS/Mhz 2.70 Coremark/Mhz,, 16KB-I$,16KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) -> - Artix 7 -> 140 Mhz 1767 LUT 1128 FF - Cyclone V -> 90 Mhz 1,089 ALMs - Cyclone IV -> 79 Mhz 2,336 LUT 1,048 FF +VexRiscv full max perf (HZ*IPC) -> (RV32IM, 1.38 DMIPS/Mhz 2.57 Coremark/Mhz, 8KB-I$,8KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch prediction in the fetch stage, branch and shift operations done in the Execute stage) -> + Artix 7 -> 200 Mhz 1935 LUT 1216 FF + Cyclone V -> 130 Mhz 1,166 ALMs + Cyclone IV -> 126 Mhz 2,484 LUT 1,120 FF VexRiscv full with MMU (RV32IM, 1.24 DMIPS/Mhz 2.35 Coremark/Mhz, with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, debug module, catch exceptions, dynamic branch, MMU) -> - Artix 7 -> 161 Mhz 1985 LUT 1585 FF - Cyclone V -> 124 Mhz 1,319 ALMs - Cyclone IV -> 122 Mhz 2,710 LUT 1,501 FF + Artix 7 -> 151 Mhz 2021 LUT 1541 FF + Cyclone V -> 124 Mhz 1,368 ALMs + Cyclone IV -> 128 Mhz 2,826 LUT 1,474 FF VexRiscv linux balanced (RV32IMA, 1.21 DMIPS/Mhz 2.27 Coremark/Mhz, with cache trashing, 4KB-I$, 4KB-D$, single cycle barrel shifter, catch exceptions, static branch, MMU, Supervisor, Compatible with mainstream linux) -> - Artix 7 -> 170 Mhz 2530 LUT 2013 FF - Cyclone V -> 125 Mhz 1,618 ALMs - Cyclone IV -> 116 Mhz 3,314 LUT 2,016 FF - + Artix 7 -> 180 Mhz 2883 LUT 2130 FF + Cyclone V -> 131 Mhz 1,764 ALMs + Cyclone IV -> 121 Mhz 3,608 LUT 2,082 FF ``` The following configuration results in 1.44 DMIPS/MHz: @@ -319,9 +318,9 @@ You can find some FPGA projects which instantiate the Briey SoC here (DE1-SoC, D Here are some measurements of Briey SoC timings and area : ``` - Artix 7 -> 186 Mhz 3138 LUT 3328 FF - Cyclone V -> 139 Mhz 2,175 ALMs - Cyclone IV -> 129 Mhz 4,337 LUT 3,170 FF +Artix 7 -> 181 Mhz 3220 LUT 3181 FF +Cyclone V -> 142 Mhz 2,222 ALMs +Cyclone IV -> 130 Mhz 4,538 LUT 3,211 FF ``` ## Murax SoC @@ -374,16 +373,16 @@ Here are some timing and area measurements of the Murax SoC: ``` Murax interlocked stages (0.45 DMIPS/Mhz, 8 bits GPIO) -> - Artix 7 -> 215 Mhz 1044 LUT 1202 FF - Cyclone V -> 173 Mhz 737 ALMs - Cyclone IV -> 144 Mhz 1,484 LUT 1,206 FF - iCE40 -> 64 Mhz 2422 LC (nextpnr) + Artix 7 -> 216 Mhz 1109 LUT 1201 FF + Cyclone V -> 182 Mhz 725 ALMs + Cyclone IV -> 147 Mhz 1,551 LUT 1,223 FF + iCE40 -> 64 Mhz 2422 LC (nextpnr) MuraxFast bypassed stages (0.65 DMIPS/Mhz, 8 bits GPIO) -> - Artix 7 -> 229 Mhz 1269 LUT 1302 FF - Cyclone V -> 159 Mhz 864 ALMs - Cyclone IV -> 137 Mhz 1,688 LUT 1,241 FF - iCE40 -> 66 Mhz 2799 LC (nextpnr) + Artix 7 -> 224 Mhz 1278 LUT 1300 FF + Cyclone V -> 173 Mhz 867 ALMs + Cyclone IV -> 143 Mhz 1,755 LUT 1,258 FF + iCE40 -> 66 Mhz 2799 LC (nextpnr) ``` Some scripts to generate the SoC and call the icestorm toolchain can be found here: `scripts/Murax/` diff --git a/doc/smp/smp.md b/doc/smp/smp.md index 200ebee..5e22e4d 100644 --- a/doc/smp/smp.md +++ b/doc/smp/smp.md @@ -84,6 +84,8 @@ Composed of 2 stream : Used by the interconnect to order master to change their memory copies status and get memory copies owners data. +Composed of 2 stream : + | Name | Direction | Description | |----------|-----------|----------| | probeCmd | M <- S | Used for cache management | @@ -129,7 +131,7 @@ Emitted on the readAck channel (master -> slave), it carry no information, just | Name | From command | Description | |--------------|---------------|----------| -| readSuccess | * | - | +| readSuccess | * | - | ### Write commands diff --git a/src/main/scala/vexriscv/Services.scala b/src/main/scala/vexriscv/Services.scala index 09cd098..4b0aeca 100644 --- a/src/main/scala/vexriscv/Services.scala +++ b/src/main/scala/vexriscv/Services.scala @@ -13,7 +13,6 @@ trait JumpService{ trait IBusFetcher{ def haltIt() : Unit - def flushIt() : Unit def incoming() : Bool def pcValid(stage : Stage) : Bool def getInjectionPort() : Stream[Bits] diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala index 1e38791..3350dc9 100644 --- a/src/main/scala/vexriscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -36,7 +36,6 @@ case class VexRiscvConfig(){ object PC extends Stageable(UInt(32 bits)) object PC_CALC_WITHOUT_JUMP extends Stageable(UInt(32 bits)) object INSTRUCTION extends Stageable(Bits(32 bits)) - object INSTRUCTION_READY extends Stageable(Bool) object INSTRUCTION_ANTICIPATED extends Stageable(Bits(32 bits)) object LEGAL_INSTRUCTION extends Stageable(Bool) object REGFILE_WRITE_VALID extends Stageable(Bool) diff --git a/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala b/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala index 28843d8..6c892f0 100644 --- a/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmuMaxPerf.scala @@ -20,7 +20,7 @@ object GenFullNoMmuMaxPerf extends App{ prediction = DYNAMIC_TARGET, historyRamSizeLog2 = 8, config = InstructionCacheConfig( - cacheSize = 4096*4, + cacheSize = 4096*2, bytePerLine =32, wayCount = 1, addressWidth = 32, @@ -29,13 +29,13 @@ object GenFullNoMmuMaxPerf extends App{ catchIllegalAccess = true, catchAccessFault = true, asyncTagMemory = false, - twoCycleRam = true, + twoCycleRam = false, twoCycleCache = true ) ), new DBusCachedPlugin( config = new DataCacheConfig( - cacheSize = 4096*4, + cacheSize = 4096*2, bytePerLine = 32, wayCount = 1, addressWidth = 32, @@ -76,7 +76,7 @@ object GenFullNoMmuMaxPerf extends App{ new CsrPlugin(CsrPluginConfig.small), new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( - earlyBranch = true, + earlyBranch = false, catchAddressMisaligned = true ), new YamlPlugin("cpu0.yaml") diff --git a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala index 89dffe0..9bca107 100644 --- a/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala +++ b/src/main/scala/vexriscv/demo/GenNoCacheNoMmuMaxPerf.scala @@ -56,7 +56,7 @@ object GenNoCacheNoMmuMaxPerf extends App{ new CsrPlugin(CsrPluginConfig.small), new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( - earlyBranch = true, + earlyBranch = false, catchAddressMisaligned = true ), new YamlPlugin("cpu0.yaml") diff --git a/src/main/scala/vexriscv/demo/Linux.scala b/src/main/scala/vexriscv/demo/Linux.scala index 906b5b2..c13ef12 100644 --- a/src/main/scala/vexriscv/demo/Linux.scala +++ b/src/main/scala/vexriscv/demo/Linux.scala @@ -272,7 +272,7 @@ object LinuxGen { // wfiGenAsNop = true, // ucycleAccess = CsrAccess.NONE // )), -// new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), + new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), new BranchPlugin( earlyBranch = false, catchAddressMisaligned = true, @@ -310,7 +310,7 @@ object LinuxGen { // } // } - SpinalConfig(mergeAsyncProcess = true, anonymSignalPrefix = "_zz").generateVerilog { + SpinalConfig(mergeAsyncProcess = false, anonymSignalPrefix = "_zz").generateVerilog { val toplevel = new VexRiscv(configFull( diff --git a/src/main/scala/vexriscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala index 08a7d72..a9961a9 100644 --- a/src/main/scala/vexriscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -4,8 +4,9 @@ import spinal.core._ import spinal.lib._ import spinal.lib.eda.bench._ import spinal.lib.eda.icestorm.IcestormStdTargets +import spinal.lib.io.InOutWrapper import vexriscv.VexRiscv -import vexriscv.plugin.{DecoderSimplePlugin} +import vexriscv.plugin.DecoderSimplePlugin import scala.collection.mutable.ArrayBuffer import scala.util.Random @@ -96,7 +97,7 @@ object VexRiscvSynthesisBench { } val full = new Rtl { - override def getName(): String = "VexRiscv full" + override def getName(): String = "VexRiscv full with MMU" override def getRtlPath(): String = "VexRiscvFull.v" SpinalVerilog(wrap(GenFull.cpu()).setDefinitionName(getRtlPath().split("\\.").head)) } @@ -113,15 +114,10 @@ object VexRiscvSynthesisBench { // val rtls = List(smallAndProductive, smallAndProductiveWithICache, fullNoMmuMaxPerf, fullNoMmu, full) // val rtls = List(smallAndProductive) - val targets = XilinxStdTargets( - vivadoArtix7Path = "/media/miaou/HD/linux/Xilinx/Vivado/2018.3/bin" - ) ++ AlteraStdTargets( - quartusCycloneIVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin", - quartusCycloneVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin" - ) ++ IcestormStdTargets().take(1) + val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1) // val targets = IcestormStdTargets() - Bench(rtls, targets, "/media/miaou/HD/linux/tmp") + Bench(rtls, targets) } } @@ -132,7 +128,7 @@ object BrieySynthesisBench { override def getName(): String = "Briey" override def getRtlPath(): String = "Briey.v" SpinalVerilog({ - val briey = new Briey(BrieyConfig.default).setDefinitionName(getRtlPath().split("\\.").head) + val briey = InOutWrapper(new Briey(BrieyConfig.default).setDefinitionName(getRtlPath().split("\\.").head)) briey.io.axiClk.setName("clk") briey }) @@ -141,14 +137,9 @@ object BrieySynthesisBench { val rtls = List(briey) - val targets = XilinxStdTargets( - vivadoArtix7Path = "/media/miaou/HD/linux/Xilinx/Vivado/2018.3/bin" - ) ++ AlteraStdTargets( - quartusCycloneIVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin", - quartusCycloneVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin" - ) + val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1) - Bench(rtls, targets, "/media/miaou/HD/linux/tmp") + Bench(rtls, targets) } } @@ -161,7 +152,7 @@ object MuraxSynthesisBench { override def getName(): String = "Murax" override def getRtlPath(): String = "Murax.v" SpinalVerilog({ - val murax = new Murax(MuraxConfig.default.copy(gpioWidth = 8)).setDefinitionName(getRtlPath().split("\\.").head) + val murax = InOutWrapper(new Murax(MuraxConfig.default.copy(gpioWidth = 8)).setDefinitionName(getRtlPath().split("\\.").head)) murax.io.mainClk.setName("clk") murax }) @@ -172,7 +163,7 @@ object MuraxSynthesisBench { override def getName(): String = "MuraxFast" override def getRtlPath(): String = "MuraxFast.v" SpinalVerilog({ - val murax = new Murax(MuraxConfig.fast.copy(gpioWidth = 8)).setDefinitionName(getRtlPath().split("\\.").head) + val murax = InOutWrapper(new Murax(MuraxConfig.fast.copy(gpioWidth = 8)).setDefinitionName(getRtlPath().split("\\.").head)) murax.io.mainClk.setName("clk") murax }) @@ -180,14 +171,9 @@ object MuraxSynthesisBench { val rtls = List(murax, muraxFast) - val targets = IcestormStdTargets().take(1) ++ XilinxStdTargets( - vivadoArtix7Path = "/media/miaou/HD/linux/Xilinx/Vivado/2018.3/bin" - ) ++ AlteraStdTargets( - quartusCycloneIVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin", - quartusCycloneVPath = "/media/miaou/HD/linux/intelFPGA_lite/18.1/quartus/bin" - ) + val targets = XilinxStdTargets() ++ AlteraStdTargets() ++ IcestormStdTargets().take(1) - Bench(rtls, targets, "/media/miaou/HD/linux/tmp") + Bench(rtls, targets) } } diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala index 0a809c6..4df0f79 100644 --- a/src/main/scala/vexriscv/ip/InstructionCache.scala +++ b/src/main/scala/vexriscv/ip/InstructionCache.scala @@ -114,7 +114,7 @@ case class InstructionCacheCpuFetch(p : InstructionCacheConfig) extends Bundle w val mmuBus = MemoryTranslatorBus() val physicalAddress = UInt(p.addressWidth bits) val cacheMiss, error, mmuRefilling, mmuException, isUser = ifGen(!p.twoCycleCache)(Bool) - val haltIt = Bool + val haltIt = Bool() //Used to wait on the MMU rsp busy override def asMaster(): Unit = { out(isValid, isStuck, isRemoved, pc) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 98dfbaa..0cdc896 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -69,6 +69,7 @@ case class CsrPluginConfig( midelegAccess : CsrAccess = CsrAccess.NONE, pipelineCsrRead : Boolean = false, pipelinedInterrupt : Boolean = true, + csrOhDecoder : Boolean = true, deterministicInteruptionEntry : Boolean = false, //Only used for simulatation purposes wfiOutput : Boolean = false ){ @@ -263,7 +264,7 @@ case class CsrReadToWriteOverride(that : Data, bitOffset : Int) //Used for speci case class CsrOnWrite(doThat :() => Unit) case class CsrOnRead(doThat : () => Unit) case class CsrMapping() extends CsrInterface{ - val mapping = mutable.HashMap[Int,ArrayBuffer[Any]]() + val mapping = mutable.LinkedHashMap[Int,ArrayBuffer[Any]]() def addMappingAt(address : Int,that : Any) = mapping.getOrElseUpdate(address,new ArrayBuffer[Any]) += that override def r(csrAddress : Int, bitOffset : Int, that : Data): Unit = addMappingAt(csrAddress, CsrRead(that,bitOffset)) override def w(csrAddress : Int, bitOffset : Int, that : Data): Unit = addMappingAt(csrAddress, CsrWrite(that,bitOffset)) @@ -447,9 +448,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep if(supervisorGen) { - redoInterface = pcManagerService.createJumpInterface(pipeline.execute) - redoInterface.valid := False - redoInterface.payload.assignDontCare() + redoInterface = pcManagerService.createJumpInterface(pipeline.execute, -1) } exceptionPendings = Vec(Bool, pipeline.stages.length) @@ -643,10 +642,13 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN) - if(supervisorGen) onWrite(CSR.SATP){ - execute.arbitration.flushNext := True - redoInterface.valid := True - redoInterface.payload := execute.input(PC) + 4 + if(supervisorGen) { + redoInterface.valid := False + redoInterface.payload := decode.input(PC) + onWrite(CSR.SATP){ + execute.arbitration.flushNext := True + redoInterface.valid := True + } } } } @@ -685,7 +687,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep //Aggregate all exception port and remove required instructions - val exceptionPortCtrl = if(exceptionPortsInfos.nonEmpty) new Area{ + val exceptionPortCtrl = exceptionPortsInfos.nonEmpty generate new Area{ val firstStageIndexWithExceptionPort = exceptionPortsInfos.map(i => indexOf(i.stage)).min val exceptionValids = Vec(stages.map(s => Bool().setPartialName(s.getName()))) val exceptionValidsRegs = Vec(stages.map(s => Reg(Bool).init(False).setPartialName(s.getName()))).allowUnsetRegToAvoidLatch @@ -762,7 +764,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep //Avoid the PC register of the last stage to change durring an exception handleing (Used to fill Xepc) stages.last.dontSample.getOrElseUpdate(PC, ArrayBuffer[Bool]()) += exceptionValids.last exceptionPendings := exceptionValidsRegs - } else null + } @@ -808,17 +810,29 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep //Used to make the pipeline empty softly (for interrupts) val pipelineLiberator = new Area{ - when(interrupt.valid && allowInterrupts){ - decode.arbitration.haltByOther := decode.arbitration.isValid + val pcValids = Vec(RegInit(False), stagesFromExecute.length) + val active = interrupt.valid && allowInterrupts && decode.arbitration.isValid + when(active){ + decode.arbitration.haltByOther := True + for((stage, reg, previous) <- (stagesFromExecute, pcValids, True :: pcValids.toList).zipped){ + when(!stage.arbitration.isStuck){ + reg := previous + } + } + } + when(!active || decode.arbitration.isRemoved) { + pcValids.foreach(_ := False) } - val done = !stagesFromExecute.map(_.arbitration.isValid).orR && fetcher.pcValid(mepcCaptureStage) +// val pcValids = for(stage <- stagesFromExecute) yield RegInit(False) clearWhen(!started) setWhen(!stage.arbitration.isValid) + val done = CombInit(pcValids.last) if(exceptionPortCtrl != null) done.clearWhen(exceptionPortCtrl.exceptionValidsRegs.tail.orR) } //Interrupt/Exception entry logic val interruptJump = Bool.addTag(Verilator.public) interruptJump := interrupt.valid && pipelineLiberator.done && allowInterrupts + if(pipelinedInterrupt) interrupt.valid clearWhen(interruptJump) //avoid double fireing val hadException = RegNext(exception) init(False) pipelineLiberator.done.clearWhen(hadException) @@ -984,7 +998,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep val imm = IMM(input(INSTRUCTION)) def writeSrc = input(SRC1) // val readDataValid = True - val readData = B(0, 32 bits) + val readData = Bits(32 bits) val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers// && readDataRegValid @@ -1030,50 +1044,84 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep //Translation of the csrMapping into real logic val csrAddress = input(INSTRUCTION)(csrRange) - Component.current.addPrePopTask(() => { - switch(csrAddress) { - for ((address, jobs) <- csrMapping.mapping) { - is(address) { - val withWrite = jobs.exists(j => j.isInstanceOf[CsrWrite] || j.isInstanceOf[CsrOnWrite]) - val withRead = jobs.exists(j => j.isInstanceOf[CsrRead] || j.isInstanceOf[CsrOnRead]) - if(withRead && withWrite) { - illegalAccess := False - } else { - if (withWrite) illegalAccess.clearWhen(input(CSR_WRITE_OPCODE)) - if (withRead) illegalAccess.clearWhen(input(CSR_READ_OPCODE)) - } + Component.current.afterElaboration{ + def doJobs(jobs : ArrayBuffer[Any]): Unit ={ + val withWrite = jobs.exists(j => j.isInstanceOf[CsrWrite] || j.isInstanceOf[CsrOnWrite]) + val withRead = jobs.exists(j => j.isInstanceOf[CsrRead] || j.isInstanceOf[CsrOnRead]) + if(withRead && withWrite) { + illegalAccess := False + } else { + if (withWrite) illegalAccess.clearWhen(input(CSR_WRITE_OPCODE)) + if (withRead) illegalAccess.clearWhen(input(CSR_READ_OPCODE)) + } - when(writeEnable) { - for (element <- jobs) element match { - case element: CsrWrite => element.that.assignFromBits(writeData(element.bitOffset, element.that.getBitsWidth bits)) - case element: CsrOnWrite => - element.doThat() - case _ => - } - } + when(writeEnable) { + for (element <- jobs) element match { + case element: CsrWrite => element.that.assignFromBits(writeData(element.bitOffset, element.that.getBitsWidth bits)) + case element: CsrOnWrite => + element.doThat() + case _ => + } + } - for (element <- jobs) element match { - case element: CsrRead if element.that.getBitsWidth != 0 => readData(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits - case _ => - } - - when(readEnable) { - for (element <- jobs) element match { - case element: CsrOnRead => - element.doThat() - case _ => - } - } + when(readEnable) { + for (element <- jobs) element match { + case element: CsrOnRead => + element.doThat() + case _ => } } } - switch(csrAddress) { - for ((address, jobs) <- csrMapping.mapping if jobs.exists(_.isInstanceOf[CsrReadToWriteOverride])) { - is(address) { - for (element <- jobs) element match { - case element: CsrReadToWriteOverride if element.that.getBitsWidth != 0 => readToWriteData(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits - case _ => + def doJobsOverride(jobs : ArrayBuffer[Any]): Unit ={ + for (element <- jobs) element match { + case element: CsrReadToWriteOverride if element.that.getBitsWidth != 0 => readToWriteData(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits + case _ => + } + } + + csrOhDecoder match { + case false => { + readData := 0 + switch(csrAddress) { + for ((address, jobs) <- csrMapping.mapping) { + is(address) { + doJobs(jobs) + for (element <- jobs) element match { + case element: CsrRead if element.that.getBitsWidth != 0 => readData(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits + case _ => + } + } + } + } + switch(csrAddress) { + for ((address, jobs) <- csrMapping.mapping if jobs.exists(_.isInstanceOf[CsrReadToWriteOverride])) { + is(address) { + doJobsOverride(jobs) + } + } + } + } + case true => { + val oh = csrMapping.mapping.keys.toList.distinct.map(address => address -> RegNextWhen(decode.input(INSTRUCTION)(csrRange) === address, !execute.arbitration.isStuck).setCompositeName(this, "csr_" + address)).toMap + val readDatas = ArrayBuffer[Bits]() + for ((address, jobs) <- csrMapping.mapping) { + when(oh(address)){ + doJobs(jobs) + } + if(jobs.exists(_.isInstanceOf[CsrRead])) { + val masked = B(0, 32 bits) + when(oh(address)) (for (element <- jobs) element match { + case element: CsrRead if element.that.getBitsWidth != 0 => masked(element.bitOffset, element.that.getBitsWidth bits) := element.that.asBits + case _ => + }) + readDatas += masked + } + } + readData := readDatas.reduceBalancedTree(_ | _) + for ((address, jobs) <- csrMapping.mapping) { + when(oh(address)){ + doJobsOverride(jobs) } } } @@ -1081,7 +1129,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep illegalAccess setWhen(privilege < csrAddress(9 downto 8).asUInt) illegalAccess clearWhen(!arbitration.isValid || !input(IS_CSR)) - }) + } } } } diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index f0eaa81..fd45dd8 100644 --- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -145,7 +145,7 @@ class DBusCachedPlugin(val config : DataCacheConfig, decoderService.add(FENCE, Nil) mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(MemoryTranslatorPort.PRIORITY_DATA ,memoryTranslatorPortConfig) - redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(if(pipeline.writeBack != null) pipeline.writeBack else pipeline.execute) + redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(if(pipeline.writeBack != null) pipeline.writeBack else pipeline.memory) if(catchSomething) exceptionBus = pipeline.service(classOf[ExceptionService]).newExceptionPort(if(pipeline.writeBack == null) pipeline.memory else pipeline.writeBack) diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala index 1b0084b..93e65e3 100644 --- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala @@ -201,7 +201,6 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : execute.arbitration.haltByOther := True busReadDataReg := execute.input(PC).asBits when(stagesFromExecute.tail.map(_.arbitration.isValid).orR === False){ - iBusFetcher.flushIt() iBusFetcher.haltIt() execute.arbitration.flushIt := True execute.arbitration.flushNext := True @@ -214,10 +213,11 @@ class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : iBusFetcher.haltIt() } - when(stepIt && iBusFetcher.incoming()) { - iBusFetcher.haltIt() + when(stepIt) { + //Assume nothing will stop the CPU in the decode stage when(decode.arbitration.isValid) { haltIt := True + decode.arbitration.flushNext := True } } diff --git a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala index a1076e7..e88a98c 100644 --- a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala @@ -172,7 +172,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false, } if(catchIllegalInstruction){ - decodeExceptionPort.valid := arbitration.isValid && input(INSTRUCTION_READY) && !input(LEGAL_INSTRUCTION) // ?? HalitIt to alow decoder stage to wait valid data from 2 stages cache cache ?? + decodeExceptionPort.valid := arbitration.isValid && !input(LEGAL_INSTRUCTION) // ?? HalitIt to alow decoder stage to wait valid data from 2 stages cache cache ?? decodeExceptionPort.code := 2 decodeExceptionPort.badAddr := input(INSTRUCTION).asUInt } diff --git a/src/main/scala/vexriscv/plugin/Fetcher.scala b/src/main/scala/vexriscv/plugin/Fetcher.scala index 8aa351e..1de5021 100644 --- a/src/main/scala/vexriscv/plugin/Fetcher.scala +++ b/src/main/scala/vexriscv/plugin/Fetcher.scala @@ -16,12 +16,14 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, val decodePcGen : Boolean, val compressedGen : Boolean, val cmdToRspStageCount : Int, - val pcRegReusedForSecondStage : Boolean, + val allowPcRegReusedForSecondStage : Boolean, val injectorReadyCutGen : Boolean, val prediction : BranchPrediction, val historyRamSizeLog2 : Int, val injectorStage : Boolean, - val relaxPredictorAddress : Boolean) extends Plugin[VexRiscv] with JumpService with IBusFetcher{ + val relaxPredictorAddress : Boolean, + val fetchRedoGen : Boolean, + val predictionBuffer : Boolean = true) extends Plugin[VexRiscv] with JumpService with IBusFetcher{ var prefetchExceptionPort : Flow[ExceptionCause] = null var decodePrediction : DecodePredictionBus = null var fetchPrediction : FetchPredictionBus = null @@ -31,7 +33,6 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, // assert(!(cmdToRspStageCount == 1 && !injectorStage)) assert(!(compressedGen && !decodePcGen)) var fetcherHalt : Bool = null - var fetcherflushIt : Bool = null var pcValids : Vec[Bool] = null def pcValid(stage : Stage) = pcValids(pipeline.indexOf(stage)) var incomingInstruction : Bool = null @@ -42,12 +43,10 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, injectionPort = Stream(Bits(32 bits)) injectionPort } - + def pcRegReusedForSecondStage = allowPcRegReusedForSecondStage && prediction != DYNAMIC_TARGET //TODO might not be required for DYNAMIC_TARGET var predictionJumpInterface : Flow[UInt] = null override def haltIt(): Unit = fetcherHalt := True - override def flushIt(): Unit = fetcherflushIt := True - case class JumpInfo(interface : Flow[UInt], stage: Stage, priority : Int) val jumpInfos = ArrayBuffer[JumpInfo]() override def createJumpInterface(stage: Stage, priority : Int = 0): Flow[UInt] = { @@ -61,7 +60,6 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, // var decodeExceptionPort : Flow[ExceptionCause] = null override def setup(pipeline: VexRiscv): Unit = { fetcherHalt = False - fetcherflushIt = False incomingInstruction = False if(resetVector == null) externalResetVector = in(UInt(32 bits).setName("externalResetVector")) @@ -75,21 +73,33 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, } case DYNAMIC_TARGET => { fetchPrediction = pipeline.service(classOf[PredictionInterface]).askFetchPrediction() - if(compressedGen && cmdToRspStageCount > 1){ - dynamicTargetFailureCorrection = createJumpInterface(pipeline.decode) - } } } pcValids = Vec(Bool, pipeline.stages.size) } + object IBUS_RSP + object DECOMPRESSOR + object INJECTOR_M2S + + def isDrivingDecode(s : Any): Boolean = { + if(injectorStage) return s == INJECTOR_M2S + s == IBUS_RSP || s == DECOMPRESSOR + } + + class FetchArea(pipeline : VexRiscv) extends Area { import pipeline._ import pipeline.config._ + val externalFlush = stages.map(_.arbitration.flushNext).orR - //JumpService hardware implementation + def getFlushAt(s : Any, lastCond : Boolean = true): Bool = { + if(isDrivingDecode(s) && lastCond) pipeline.decode.arbitration.isRemoved else externalFlush + } + + //Arbitrate jump requests into pcLoad val jump = new Area { val sortedByStage = jumpInfos.sortWith((a, b) => { (pipeline.indexOf(a.stage) > pipeline.indexOf(b.stage)) || @@ -103,7 +113,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, pcLoad.payload := MuxOH(OHMasking.first(valids.asBits), pcs) } - fetcherflushIt setWhen(stages.map(_.arbitration.flushNext).orR) + //The fetchPC pcReg can also be use for the second stage of the fetch //When the fetcherHalt is set and the pipeline isn't stalled,, the pc is propagated to to the pcReg, which allow @@ -112,12 +122,16 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, //PC calculation without Jump val output = Stream(UInt(32 bits)) val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public) - val corrected = False + val correction = False + val correctionReg = RegInit(False) setWhen(correction) clearWhen(output.fire) + val corrected = correction || correctionReg val pcRegPropagate = False val booted = RegNext(True) init (False) - val inc = RegInit(False) clearWhen(corrected || pcRegPropagate) setWhen(output.fire) clearWhen(!output.valid && output.ready) + val inc = RegInit(False) clearWhen(correction || pcRegPropagate) setWhen(output.fire) clearWhen(!output.valid && output.ready) val pc = pcReg + (inc ## B"00").asUInt val predictionPcLoad = ifGen(prediction == DYNAMIC_TARGET) (Flow(UInt(32 bits))) + val redo = (fetchRedoGen || prediction == DYNAMIC_TARGET) generate Flow(UInt(32 bits)) + val flushed = False if(compressedGen) when(inc) { pc(1) := False @@ -125,22 +139,27 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, if(predictionPcLoad != null) { when(predictionPcLoad.valid) { - corrected := True + correction := True pc := predictionPcLoad.payload } } + if(redo != null) when(redo.valid){ + correction := True + pc := redo.payload + flushed := True + } when(jump.pcLoad.valid) { - corrected := True + correction := True pc := jump.pcLoad.payload + flushed := True } - - when(booted && (output.ready || fetcherflushIt || pcRegPropagate)){ + when(booted && (output.ready || correction || pcRegPropagate)){ pcReg := pc } pc(0) := False - if(!pipeline(RVC_GEN)) pc(1) := False + if(!compressedGen) pc(1) := False output.valid := !fetcherHalt && booted output.payload := pc @@ -148,6 +167,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, val decodePc = ifGen(decodePcGen)(new Area { //PC calculation without Jump + val flushed = False val pcReg = Reg(UInt(32 bits)) init(if(resetVector != null) resetVector else externalResetVector) addAttribute(Verilator.public) val pcPlus = if(compressedGen) pcReg + ((decode.input(IS_RVC)) ? U(2) | U(4)) @@ -170,6 +190,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, //application of the selected jump request when(jump.pcLoad.valid && (!decode.arbitration.isStuck || decode.arbitration.isRemoved)) { pcReg := jump.pcLoad.payload + flushed := True } }) @@ -177,116 +198,109 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, case class FetchRsp() extends Bundle { val pc = UInt(32 bits) val rsp = IBusSimpleRsp() - val isRvc = Bool + val isRvc = Bool() } val iBusRsp = new Area { -// val input = Stream(UInt(32 bits)) -// val inputPipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount) -// val inputPipelineHalt = Vec(False, cmdToRspStageCount-1) -// for(i <- 0 until cmdToRspStageCount) { -// inputPipeline(i) << {i match { -// case 0 => input.m2sPipeWithFlush(flush, false, collapsBubble = false) -// case _ => inputPipeline(i-1).haltWhen(inputPipelineHalt(i-1)).m2sPipeWithFlush(flush,collapsBubble = false) -// }} -// } - -// val stages = Array.fill(cmdToRspStageCount)(Stream(UInt(32 bits))) + val redoFetch = False val stages = Array.fill(cmdToRspStageCount + 1)(new Bundle { val input = Stream(UInt(32 bits)) val output = Stream(UInt(32 bits)) - val halt = Bool - val inputSample = Bool + val halt = Bool() }) stages(0).input << fetchPc.output - stages(0).inputSample := True for(s <- stages) { s.halt := False s.output << s.input.haltWhen(s.halt) } + if(fetchPc.redo != null) { + fetchPc.redo.valid := redoFetch + fetchPc.redo.payload := stages.last.input.payload + } + + val flush = (if(isDrivingDecode(IBUS_RSP)) pipeline.decode.arbitration.isRemoved || decode.arbitration.flushNext && !decode.arbitration.isStuck else externalFlush) || redoFetch for((s,sNext) <- (stages, stages.tail).zipped) { + val sFlushed = if(s != stages.head) flush else False + val sNextFlushed = flush if(s == stages.head && pcRegReusedForSecondStage) { - sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(fetcherflushIt, s != stages.head, collapsBubble = false)) + sNext.input.arbitrationFrom(s.output.toEvent().m2sPipeWithFlush(sNextFlushed, false, collapsBubble = false, flushInput = sFlushed)) sNext.input.payload := fetchPc.pcReg fetchPc.pcRegPropagate setWhen(sNext.input.ready) } else { - sNext.input << s.output.m2sPipeWithFlush(fetcherflushIt, s != stages.head, collapsBubble = false) + sNext.input << s.output.m2sPipeWithFlush(sNextFlushed, false, collapsBubble = false, flushInput = sFlushed) } } -// -// val pipeline = Vec(Stream(UInt(32 bits)), cmdToRspStageCount + 1) -// val halts = Vec(False, cmdToRspStageCount) -// for(i <- 0 until cmdToRspStageCount + 1) { -// pipeline(i) << {i match { -// case 0 => pipeline(0) << fetchPc.output.haltWhen(halts(i)) -// case 1 => pipeline(1).m2sPipeWithFlush(flush, false, collapsBubble = false) -// case _ => inputPipeline(i-1).haltWhen(inputPipelineHalt(i-1)).m2sPipeWithFlush(flush,collapsBubble = false) -// }} -// } - - // ... - val readyForError = True val output = Stream(FetchRsp()) incomingInstruction setWhen(stages.tail.map(_.input.valid).reduce(_ || _)) } val decompressor = ifGen(decodePcGen)(new Area{ - def input = iBusRsp.output + val input = iBusRsp.output.clearValidWhen(iBusRsp.redoFetch) val output = Stream(FetchRsp()) + val flush = getFlushAt(DECOMPRESSOR) + val flushNext = if(isDrivingDecode(DECOMPRESSOR)) decode.arbitration.flushNext else False + val consumeCurrent = if(isDrivingDecode(DECOMPRESSOR)) flushNext && output.ready else False val bufferValid = RegInit(False) val bufferData = Reg(Bits(16 bits)) + val isInputLowRvc = input.rsp.inst(1 downto 0) =/= 3 + val isInputHighRvc = input.rsp.inst(17 downto 16) =/= 3 + val throw2BytesReg = RegInit(False) + val throw2Bytes = throw2BytesReg || input.pc(1) + val unaligned = throw2Bytes || bufferValid + def aligned = !unaligned val raw = Mux( sel = bufferValid, whenTrue = input.rsp.inst(15 downto 0) ## bufferData, - whenFalse = input.rsp.inst(31 downto 16) ## (input.pc(1) ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0)) + whenFalse = input.rsp.inst(31 downto 16) ## (throw2Bytes ? input.rsp.inst(31 downto 16) | input.rsp.inst(15 downto 0)) ) val isRvc = raw(1 downto 0) =/= 3 val decompressed = RvcDecompressor(raw(15 downto 0)) - output.valid := (isRvc ? (bufferValid || input.valid) | (input.valid && (bufferValid || !input.pc(1)))) + output.valid := input.valid && !(throw2Bytes && !bufferValid && !isInputHighRvc) output.pc := input.pc output.isRvc := isRvc output.rsp.inst := isRvc ? decompressed | raw -// input.ready := (bufferValid ? (!isRvc && output.ready) | (input.pc(1) || output.ready)) - input.ready := !output.valid || !(!output.ready || (isRvc && !input.pc(1) && input.rsp.inst(16, 2 bits) =/= 3) || (!isRvc && bufferValid && input.rsp.inst(16, 2 bits) =/= 3)) - addPrePopTask(() => { - when(!input.ready && output.fire && !fetcherflushIt /* && ((isRvc && !bufferValid && !input.pc(1)) || (!isRvc && bufferValid && input.rsp.inst(16, 2 bits) =/= 3))*/) { - input.pc.getDrivingReg(1) := True - } - }) + input.ready := output.ready && (!iBusRsp.stages.last.input.valid || flushNext || (!(bufferValid && isInputHighRvc) && !(aligned && isInputLowRvc && isInputHighRvc))) - bufferValid clearWhen(output.fire) - val bufferFill = False - when(input.fire){ - when(!(!isRvc && !input.pc(1) && !bufferValid) && !(isRvc && input.pc(1) && output.ready)) { - bufferValid := True - bufferFill := True - } otherwise { - bufferValid := False - } - bufferData := input.rsp.inst(31 downto 16) + when(output.fire){ + throw2BytesReg := (aligned && isInputLowRvc && isInputHighRvc) || (bufferValid && isInputHighRvc) + } + val bufferFill = (aligned && isInputLowRvc && !isInputHighRvc) || (bufferValid && !isInputHighRvc) || (throw2Bytes && !isRvc && !isInputHighRvc) + when(output.ready && input.valid){ + bufferValid := False + } + when(output.ready && input.valid){ + bufferData := input.rsp.inst(31 downto 16) + bufferValid setWhen(bufferFill) + } + + when(flush || consumeCurrent){ + throw2BytesReg := False + bufferValid := False + } + + if(fetchPc.redo != null) { + fetchPc.redo.payload(1) setWhen(throw2BytesReg) } - bufferValid.clearWhen(fetcherflushIt) - iBusRsp.readyForError.clearWhen(bufferValid && isRvc) //Can't emit error, as there is a earlier instruction pending - incomingInstruction setWhen(bufferValid && bufferData(1 downto 0) =/= 3) }) def condApply[T](that : T, cond : Boolean)(func : (T) => T) = if(cond)func(that) else that val injector = new Area { - val inputBeforeStage = condApply(if (decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(fetcherflushIt)) + val inputBeforeStage = condApply(if (decodePcGen) decompressor.output else iBusRsp.output, injectorReadyCutGen)(_.s2mPipe(externalFlush)) if (injectorReadyCutGen) { iBusRsp.readyForError.clearWhen(inputBeforeStage.valid) //Can't emit error if there is a instruction pending in the s2mPipe incomingInstruction setWhen (inputBeforeStage.valid) } val decodeInput = (if (injectorStage) { - val decodeInput = inputBeforeStage.m2sPipeWithFlush(fetcherflushIt, collapsBubble = false) + val flushStage = getFlushAt(INJECTOR_M2S) + val decodeInput = inputBeforeStage.m2sPipeWithFlush(flushStage, false, collapsBubble = false, flushInput = externalFlush) decode.insert(INSTRUCTION_ANTICIPATED) := Mux(decode.arbitration.isStuck, decode.input(INSTRUCTION), inputBeforeStage.rsp.inst) iBusRsp.readyForError.clearWhen(decodeInput.valid) //Can't emit error when there is a instruction pending in the injector stage buffer incomingInstruction setWhen (decodeInput.valid) @@ -298,16 +312,16 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, if(!decodePcGen) iBusRsp.readyForError.clearWhen(!pcValid(decode)) //Need to wait a valid PC on the decode stage, as it is use to fill CSR xEPC - def pcUpdatedGen(input : Bool, stucks : Seq[Bool], relaxedInput : Boolean) : Seq[Bool] = { + def pcUpdatedGen(input : Bool, stucks : Seq[Bool], relaxedInput : Boolean, flush : Bool) : Seq[Bool] = { stucks.scanLeft(input)((i, stuck) => { val reg = RegInit(False) - if(!relaxedInput) when(fetcherflushIt) { + if(!relaxedInput) when(flush) { reg := False } when(!stuck) { reg := i } - if(relaxedInput || i != input) when(fetcherflushIt) { + if(relaxedInput || i != input) when(flush) { reg := False } reg @@ -316,20 +330,17 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, val stagesFromExecute = stages.dropWhile(_ != execute).toList val nextPcCalc = if (decodePcGen) new Area{ - val valids = pcUpdatedGen(True, False :: stagesFromExecute.map(_.arbitration.isStuck), true) + val valids = pcUpdatedGen(True, False :: stagesFromExecute.map(_.arbitration.isStuck), true, decodePc.flushed) pcValids := Vec(valids.takeRight(stages.size)) } else new Area{ - val valids = pcUpdatedGen(True, iBusRsp.stages.tail.map(!_.input.ready) ++ (if (injectorStage) List(!decodeInput.ready) else Nil) ++ stagesFromExecute.map(_.arbitration.isStuck), false) + val valids = pcUpdatedGen(True, iBusRsp.stages.tail.map(!_.input.ready) ++ (if (injectorStage) List(!decodeInput.ready) else Nil) ++ stagesFromExecute.map(_.arbitration.isStuck), false, fetchPc.flushed) pcValids := Vec(valids.takeRight(stages.size)) } - val decodeRemoved = RegInit(False) setWhen(decode.arbitration.isRemoved) clearWhen(fetcherflushIt) //!decode.arbitration.isStuck || decode.arbitration.isFlushed - decodeInput.ready := !decode.arbitration.isStuck - decode.arbitration.isValid := decodeInput.valid && !decodeRemoved + decode.arbitration.isValid := decodeInput.valid decode.insert(PC) := (if (decodePcGen) decodePc.pcReg else decodeInput.pc) decode.insert(INSTRUCTION) := decodeInput.rsp.inst - decode.insert(INSTRUCTION_READY) := True if (compressedGen) decode.insert(IS_RVC) := decodeInput.isRvc if (injectionPort != null) { @@ -415,18 +426,15 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, } } - def stage1ToInjectorPipe[T <: Data](input : T): (T,T) ={ + def stage1ToInjectorPipe[T <: Data](input : T): (T, T, T) ={ val iBusRspContext = iBusRsp.stages.drop(1).dropRight(1).foldLeft(input)((data,stage) => RegNextWhen(data, stage.output.ready)) -// val decompressorContext = ifGen(compressedGen)(new Area{ -// val lastContext = RegNextWhen(iBusRspContext, decompressor.input.fire) -// val output = decompressor.bufferValid ? lastContext | iBusRspContext -// }) - val decompressorContext = cloneOf(input) - decompressorContext := iBusRspContext - val injectorContext = Delay(if(compressedGen) decompressorContext else iBusRspContext, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready) + + val iBusRspContextOutput = cloneOf(input) + iBusRspContextOutput := iBusRspContext + val injectorContext = Delay(iBusRspContextOutput, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready) val injectorContextWire = cloneOf(input) //Allow combinatorial override injectorContextWire := injectorContext - (ifGen(compressedGen)(decompressorContext), injectorContextWire) + (iBusRspContext, iBusRspContextOutput, injectorContextWire) } val predictor = prediction match { @@ -449,10 +457,10 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, } val fetchContext = DynamicContext() fetchContext.hazard := hazard - fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt) + fetchContext.line := historyCache.readSync((fetchPc.output.payload >> 2).resized, iBusRsp.stages(0).output.ready || externalFlush) object PREDICTION_CONTEXT extends Stageable(DynamicContext()) - decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._2 + decode.insert(PREDICTION_CONTEXT) := stage1ToInjectorPipe(fetchContext)._3 val decodeContextPrediction = decode.input(PREDICTION_CONTEXT).line.history.msb val branchStage = decodePrediction.stage @@ -488,13 +496,11 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, } //TODO no more fireing depedancies - predictionJumpInterface.valid := decode.arbitration.isValid && decodePrediction.cmd.hadBranch //TODO OH Doublon de priorité + predictionJumpInterface.valid := decode.arbitration.isValid && decodePrediction.cmd.hadBranch predictionJumpInterface.payload := decode.input(PC) + ((decode.input(BRANCH_CTRL) === BranchCtrlEnum.JAL) ? imm.j_sext | imm.b_sext).asUInt - if(relaxPredictorAddress) KeepAttribute(predictionJumpInterface.payload) + decode.arbitration.flushNext setWhen(predictionJumpInterface.valid) - when(predictionJumpInterface.valid && decode.arbitration.isFiring){ - flushIt() - } + if(relaxPredictorAddress) KeepAttribute(predictionJumpInterface.payload) } case DYNAMIC_TARGET => new Area{ // assert(!compressedGen || cmdToRspStageCount == 1, "Can't combine DYNAMIC_TARGET and RVC as it could stop the instruction fetch mid-air") @@ -502,26 +508,40 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, case class BranchPredictorLine() extends Bundle{ val source = Bits(30 - historyRamSizeLog2 bits) val branchWish = UInt(2 bits) + val last2Bytes = ifGen(compressedGen)(Bool) val target = UInt(32 bits) - val unaligned = ifGen(compressedGen)(Bool) } val history = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) - val historyWrite = history.writePort + val historyWriteDelayPatched = history.writePort + val historyWrite = cloneOf(historyWriteDelayPatched) + historyWriteDelayPatched.valid := historyWrite.valid + historyWriteDelayPatched.address := (if(predictionBuffer) historyWrite.address - 1 else historyWrite.address) + historyWriteDelayPatched.data := historyWrite.data - val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready || fetcherflushIt) - val hit = line.source === (iBusRsp.stages(1).input.payload.asBits >> 2 + historyRamSizeLog2) && (if(compressedGen)(!(!line.unaligned && iBusRsp.stages(1).input.payload(1))) else True) - //Avoid stoping instruction fetch in the middle patch - if(compressedGen && cmdToRspStageCount == 1){ - hit clearWhen(!decompressor.output.valid) - } + val writeLast = RegNextWhen(historyWriteDelayPatched, iBusRsp.stages(0).output.ready) //Avoid write to read hazard - val historyWriteLast = RegNextWhen(historyWrite, iBusRsp.stages(0).output.ready) - val hazard = historyWriteLast.valid && historyWriteLast.address === (iBusRsp.stages(1).input.payload >> 2).resized - //TODO improve predictionPcLoad way of doing things - fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).output.valid //XXX && !(!line.unaligned && iBusRsp.inputPipeline(0).payload(1)) + val buffer = predictionBuffer generate new Area{ + val line = history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, iBusRsp.stages(0).output.ready) + val pcCorrected = RegNextWhen(fetchPc.corrected, iBusRsp.stages(0).input.ready) + val hazard = (writeLast.valid && writeLast.address === (iBusRsp.stages(1).input.payload >> 2).resized) + } + + val (line, hazard) = predictionBuffer match { + case true => + (RegNextWhen(buffer.line, iBusRsp.stages(0).output.ready), + RegNextWhen(buffer.hazard, iBusRsp.stages(0).output.ready) || buffer.pcCorrected) + case false => + (history.readSync((iBusRsp.stages(0).input.payload >> 2).resized, + iBusRsp.stages(0).output.ready), writeLast.valid && writeLast.address === (iBusRsp.stages(1).input.payload >> 2).resized) + } + + val hit = line.source === (iBusRsp.stages(1).input.payload.asBits >> 2 + historyRamSizeLog2) + if(compressedGen) hit clearWhen(!line.last2Bytes && iBusRsp.stages(1).input.payload(1)) + + fetchPc.predictionPcLoad.valid := line.branchWish.msb && hit && !hazard && iBusRsp.stages(1).input.valid fetchPc.predictionPcLoad.payload := line.target case class PredictionResult() extends Bundle{ @@ -535,22 +555,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, fetchContext.hit := hit fetchContext.line := line - val (decompressorContext, injectorContext) = stage1ToInjectorPipe(fetchContext) - if(compressedGen) { - //prediction hit on the right instruction into words - decompressorContext.hit clearWhen(decompressorContext.line.unaligned && (decompressor.bufferValid || (decompressor.isRvc && !decompressor.input.pc(1)))) - - // if(compressedGen) injectorContext.hit clearWhen(decodePc.pcReg(1) =/= injectorContext.line.unaligned) - - decodePc.predictionPcLoad.valid := injectorContext.line.branchWish.msb && injectorContext.hit && !injectorContext.hazard && injector.decodeInput.fire - decodePc.predictionPcLoad.payload := injectorContext.line.target - - - when(decompressorContext.line.branchWish.msb && decompressorContext.hit && !decompressorContext.hazard && decompressor.output.fire){ - decompressor.bufferValid := False - decompressor.input.ready := True - } - } + val (iBusRspContext, iBusRspContextOutput, injectorContext) = stage1ToInjectorPipe(fetchContext) object PREDICTION_CONTEXT extends Stageable(PredictionResult()) pipeline.decode.insert(PREDICTION_CONTEXT) := injectorContext @@ -565,7 +570,7 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, historyWrite.address := fetchPrediction.rsp.sourceLastWord(2, historyRamSizeLog2 bits) historyWrite.data.source := fetchPrediction.rsp.sourceLastWord.asBits >> 2 + historyRamSizeLog2 historyWrite.data.target := fetchPrediction.rsp.finalPc - if(compressedGen) historyWrite.data.unaligned := !fetchPrediction.stage.input(PC)(1) ^ fetchPrediction.stage.input(IS_RVC) + if(compressedGen) historyWrite.data.last2Bytes := fetchPrediction.stage.input(PC)(1) && fetchPrediction.stage.input(IS_RVC) when(fetchPrediction.rsp.wasRight) { historyWrite.valid := branchContext.hit @@ -582,27 +587,31 @@ abstract class IBusFetcherImpl(val resetVector : BigInt, historyWrite.valid clearWhen(branchContext.hazard || !branchStage.arbitration.isFiring) + val compressor = compressedGen generate new Area{ + val predictionBranch = iBusRspContext.hit && !iBusRspContext.hazard && iBusRspContext.line.branchWish(1) + val unalignedWordIssue = iBusRsp.output.valid && predictionBranch && iBusRspContext.line.last2Bytes && Mux(decompressor.unaligned, !decompressor.isInputHighRvc, decompressor.isInputLowRvc && !decompressor.isInputHighRvc) - - val predictionFailure = ifGen(compressedGen && cmdToRspStageCount > 1)(new Area{ - val predictionBranch = decompressorContext.hit && !decompressorContext.hazard && decompressorContext.line.branchWish(1) - val unalignedWordIssue = decompressor.bufferFill && decompressor.input.rsp.inst(17 downto 16) === 3 && predictionBranch - val decompressorFailure = RegInit(False) setWhen(unalignedWordIssue) clearWhen(fetcherflushIt) - val injectorFailure = Delay(decompressorFailure, cycleCount=if(injectorStage) 1 else 0, when=injector.decodeInput.ready) - val bypassFailure = if(!injectorStage) False else decompressorFailure && !injector.decodeInput.valid - - dynamicTargetFailureCorrection.valid := False - dynamicTargetFailureCorrection.payload := decode.input(PC) - when(injectorFailure || bypassFailure){ + when(unalignedWordIssue){ historyWrite.valid := True - historyWrite.address := (decode.input(PC) >> 2).resized + historyWrite.address := (iBusRsp.stages(1).input.payload >> 2).resized historyWrite.data.branchWish := 0 - decode.arbitration.isValid := False - decode.arbitration.flushNext := True - dynamicTargetFailureCorrection.valid := True + iBusRsp.redoFetch := True } - }) + + //Do not trigger prediction hit when it is one for the upper RVC word and we aren't there yet + iBusRspContextOutput.hit clearWhen(iBusRspContext.line.last2Bytes && (decompressor.bufferValid || (!decompressor.throw2Bytes && decompressor.isInputLowRvc))) + + decodePc.predictionPcLoad.valid := injectorContext.line.branchWish.msb && injectorContext.hit && !injectorContext.hazard && injector.decodeInput.fire + decodePc.predictionPcLoad.payload := injectorContext.line.target + + //Clean the RVC buffer when a prediction was made + when(iBusRspContext.line.branchWish.msb && iBusRspContextOutput.hit && !iBusRspContext.hazard && decompressor.output.fire){ + decompressor.bufferValid := False + decompressor.throw2BytesReg := False + decompressor.input.ready := True //Drop the remaining byte if any + } + } } } diff --git a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index 8ef10b2..642fcbb 100644 --- a/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -35,18 +35,21 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, memoryTranslatorPortConfig : Any = null, injectorStage : Boolean = false, withoutInjectorStage : Boolean = false, - relaxPredictorAddress : Boolean = true) extends IBusFetcherImpl( + relaxPredictorAddress : Boolean = true, + predictionBuffer : Boolean = true) extends IBusFetcherImpl( resetVector = resetVector, keepPcPlus4 = keepPcPlus4, decodePcGen = compressedGen, compressedGen = compressedGen, cmdToRspStageCount = (if(config.twoCycleCache) 2 else 1) + (if(relaxedPcCalculation) 1 else 0), - pcRegReusedForSecondStage = true, + allowPcRegReusedForSecondStage = true, injectorReadyCutGen = false, prediction = prediction, historyRamSizeLog2 = historyRamSizeLog2, injectorStage = (!config.twoCycleCache && !withoutInjectorStage) || injectorStage, - relaxPredictorAddress = relaxPredictorAddress){ + relaxPredictorAddress = relaxPredictorAddress, + fetchRedoGen = true, + predictionBuffer = predictionBuffer){ import config._ assert(isPow2(cacheSize)) @@ -58,7 +61,6 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, var iBus : InstructionCacheMemBus = null var mmuBus : MemoryTranslatorBus = null var privilegeService : PrivilegeService = null - var redoBranch : Flow[UInt] = null var decodeExceptionPort : Flow[ExceptionCause] = null val tightlyCoupledPorts = ArrayBuffer[TightlyCoupledPort]() def tightlyGen = tightlyCoupledPorts.nonEmpty @@ -86,9 +88,6 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, FLUSH_ALL -> True )) - - redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(pipeline.decode, priority = 1) //Priority 1 will win against branch predictor - if(catchSomething) { val exceptionService = pipeline.service(classOf[ExceptionService]) decodeExceptionPort = exceptionService.newExceptionPort(pipeline.decode,1) @@ -157,7 +156,7 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, stages(0).halt setWhen (cache.io.cpu.prefetch.haltIt) - cache.io.cpu.fetch.isRemoved := fetcherflushIt + cache.io.cpu.fetch.isRemoved := externalFlush } @@ -237,19 +236,9 @@ class IBusCachedPlugin(resetVector : BigInt = 0x80000000l, decodeExceptionPort.code := 1 } - when(!iBusRsp.readyForError){ - redoFetch := False - cache.io.cpu.fill.valid := False + when(redoFetch) { + iBusRsp.redoFetch := True } -// when(pipeline.stages.map(_.arbitration.flushIt).orR){ -// cache.io.cpu.fill.valid := False -// } - - - - redoBranch.valid := redoFetch - redoBranch.payload := (if (decodePcGen) decode.input(PC) else cacheRsp.pc) - decode.arbitration.flushNext setWhen(redoBranch.valid) cacheRspArbitration.halt setWhen (issueDetected || iBusRspOutputHalt) diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 7936f17..b8bc978 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -233,27 +233,31 @@ class IBusSimplePlugin( resetVector : BigInt, val rspHoldValue : Boolean = false, val singleInstructionPipeline : Boolean = false, val memoryTranslatorPortConfig : Any = null, - relaxPredictorAddress : Boolean = true + relaxPredictorAddress : Boolean = true, + predictionBuffer : Boolean = true ) extends IBusFetcherImpl( resetVector = resetVector, keepPcPlus4 = keepPcPlus4, decodePcGen = compressedGen, compressedGen = compressedGen, cmdToRspStageCount = busLatencyMin + (if(cmdForkOnSecondStage) 1 else 0), - pcRegReusedForSecondStage = !(cmdForkOnSecondStage && cmdForkPersistence), + allowPcRegReusedForSecondStage = !(cmdForkOnSecondStage && cmdForkPersistence), injectorReadyCutGen = false, prediction = prediction, historyRamSizeLog2 = historyRamSizeLog2, injectorStage = injectorStage, - relaxPredictorAddress = relaxPredictorAddress){ + relaxPredictorAddress = relaxPredictorAddress, + fetchRedoGen = memoryTranslatorPortConfig != null, + predictionBuffer = predictionBuffer){ var iBus : IBusSimpleBus = null var decodeExceptionPort : Flow[ExceptionCause] = null val catchSomething = memoryTranslatorPortConfig != null || catchAccessFault var mmuBus : MemoryTranslatorBus = null - var redoBranch : Flow[UInt] = null - if(rspHoldValue) assert(busLatencyMin <= 1) +// if(rspHoldValue) assert(busLatencyMin <= 1) + assert(!rspHoldValue, "rspHoldValue not supported yet") + assert(!singleInstructionPipeline) override def setup(pipeline: VexRiscv): Unit = { super.setup(pipeline) @@ -268,7 +272,6 @@ class IBusSimplePlugin( resetVector : BigInt, if(memoryTranslatorPortConfig != null) { mmuBus = pipeline.service(classOf[MemoryTranslator]).newTranslationPort(MemoryTranslatorPort.PRIORITY_INSTRUCTION, memoryTranslatorPortConfig) - redoBranch = pipeline.service(classOf[JumpService]).createJumpInterface(pipeline.decode, priority = 1) //Priority 1 will win against branch predictor } } @@ -282,9 +285,12 @@ class IBusSimplePlugin( resetVector : BigInt, iBus.cmd << (if(cmdWithS2mPipe) cmd.s2mPipe() else cmd) //Avoid sending to many iBus cmd - val pendingCmd = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0) - val pendingCmdNext = pendingCmd + cmd.fire.asUInt - iBus.rsp.fire.asUInt - pendingCmd := pendingCmdNext + val pending = new Area{ + val inc, dec = Bool() + val value = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0) + val next = value + U(inc) - U(dec) + value := next + } val secondStagePersistence = cmdForkPersistence && cmdForkOnSecondStage && !cmdWithS2mPipe def cmdForkStage = if(!secondStagePersistence) iBusRsp.stages(if(cmdForkOnSecondStage) 1 else 0) else iBusRsp.stages(1) @@ -292,41 +298,43 @@ class IBusSimplePlugin( resetVector : BigInt, val cmdFork = if(!secondStagePersistence) new Area { //This implementation keep the cmd on the bus until it's executed or the the pipeline is flushed def stage = cmdForkStage - stage.halt setWhen(stage.input.valid && (!cmd.valid || !cmd.ready)) - if(singleInstructionPipeline) { - cmd.valid := stage.input.valid && pendingCmd =/= pendingMax && !stages.map(_.arbitration.isValid).orR - assert(injectorStage == false) - assert(iBusRsp.stages.dropWhile(_ != stage).length <= 2) - }else { - cmd.valid := stage.input.valid && stage.output.ready && pendingCmd =/= pendingMax - } + val canEmit = stage.output.ready && pending.value =/= pendingMax + stage.halt setWhen(stage.input.valid && (!canEmit || !cmd.ready)) + cmd.valid := stage.input.valid && canEmit + pending.inc := cmd.fire } else new Area{ //This implementation keep the cmd on the bus until it's executed, even if the pipeline is flushed def stage = cmdForkStage - val pendingFull = pendingCmd === pendingMax - val cmdKeep = RegInit(False) setWhen(cmd.valid) clearWhen(cmd.ready) + val pendingFull = pending.value === pendingMax + val enterTheMarket = Bool() + val cmdKeep = RegInit(False) setWhen(enterTheMarket) clearWhen(cmd.ready) val cmdFired = RegInit(False) setWhen(cmd.fire) clearWhen(stage.input.ready) - stage.halt setWhen(cmd.isStall || (pendingFull && !cmdFired)) - cmd.valid := (stage.input.valid || cmdKeep) && !pendingFull && !cmdFired + enterTheMarket := stage.input.valid && !pendingFull && !cmdFired && !cmdKeep +// stage.halt setWhen(cmd.isStall || (pendingFull && !cmdFired)) //(cmd.isStall) + stage.halt setWhen(pendingFull && !cmdFired && !cmdKeep) + stage.halt setWhen(!cmd.ready && !cmdFired) + cmd.valid := enterTheMarket || cmdKeep + pending.inc := enterTheMarket } val mmu = (mmuBus != null) generate new Area { mmuBus.cmd.isValid := cmdForkStage.input.valid mmuBus.cmd.virtualAddress := cmdForkStage.input.payload mmuBus.cmd.bypassTranslation := False - mmuBus.end := cmdForkStage.output.fire || fetcherflushIt + mmuBus.end := cmdForkStage.output.fire || externalFlush cmd.pc := mmuBus.rsp.physicalAddress(31 downto 2) @@ U"00" - //do not emit memory request if MMU miss - when(mmuBus.rsp.exception || mmuBus.rsp.refilling){ - cmdForkStage.halt := False - cmd.valid := False - } - - when(mmuBus.busy){ - cmdForkStage.input.valid := False - cmdForkStage.input.ready := False + //do not emit memory request if MMU had issues + when(cmdForkStage.input.valid) { + when(mmuBus.rsp.refilling) { + cmdForkStage.halt := True + cmd.valid := False + } + when(mmuBus.rsp.exception) { + cmdForkStage.halt := False + cmd.valid := False + } } val joinCtx = stageXToIBusRsp(cmdForkStage, mmuBus.rsp) @@ -339,51 +347,43 @@ class IBusSimplePlugin( resetVector : BigInt, val rspJoin = new Area { import iBusRsp._ //Manage flush for iBus transactions in flight - val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0) - discardCounter := discardCounter - (iBus.rsp.fire && discardCounter =/= 0).asUInt - when(fetcherflushIt) { - if(secondStagePersistence) - discardCounter := pendingCmd + cmd.valid.asUInt - iBus.rsp.fire.asUInt - else - discardCounter := (if(cmdForkOnSecondStage) pendingCmdNext else pendingCmd - iBus.rsp.fire.asUInt) - } - - val rspBufferOutput = Stream(IBusSimpleRsp()) - - val rspBuffer = if(!rspHoldValue) new Area{ + val rspBuffer = new Area { + val output = Stream(IBusSimpleRsp()) val c = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0)) - c.io.push << iBus.rsp.throwWhen(discardCounter =/= 0).toStream - c.io.flush := fetcherflushIt - rspBufferOutput << c.io.pop - } else new Area{ - val rspStream = iBus.rsp.throwWhen(discardCounter =/= 0).toStream - val validReg = RegInit(False) setWhen(rspStream.valid) clearWhen(rspBufferOutput.ready) - rspBufferOutput << rspStream - rspBufferOutput.valid setWhen(validReg) + val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0) + discardCounter := discardCounter - (c.io.pop.valid && discardCounter =/= 0).asUInt + when(iBusRsp.flush) { + discardCounter := (if(cmdForkOnSecondStage) pending.next else pending.value - U(pending.dec)) + } + + c.io.push << iBus.rsp.toStream +// if(compressedGen) c.io.flush setWhen(decompressor.consumeCurrent) +// if(!compressedGen && isDrivingDecode(IBUS_RSP)) c.io.flush setWhen(decode.arbitration.flushNext && iBusRsp.output.ready) + val flush = discardCounter =/= 0 || iBusRsp.flush + output.valid := c.io.pop.valid && discardCounter === 0 + output.payload := c.io.pop.payload + c.io.pop.ready := output.ready || flush + + pending.dec := c.io.pop.fire // iBus.rsp.valid && flush || c.io.pop.valid && output.ready instead to avoid unecessary dependancies ? } val fetchRsp = FetchRsp() fetchRsp.pc := stages.last.output.payload - fetchRsp.rsp := rspBufferOutput.payload - fetchRsp.rsp.error.clearWhen(!rspBufferOutput.valid) //Avoid interference with instruction injection from the debug plugin - + fetchRsp.rsp := rspBuffer.output.payload + fetchRsp.rsp.error.clearWhen(!rspBuffer.output.valid) //Avoid interference with instruction injection from the debug plugin val join = Stream(FetchRsp()) val exceptionDetected = False - val redoRequired = False - join.valid := stages.last.output.valid && rspBufferOutput.valid + join.valid := stages.last.output.valid && rspBuffer.output.valid join.payload := fetchRsp stages.last.output.ready := stages.last.output.valid ? join.fire | join.ready - rspBufferOutput.ready := join.fire - output << join.haltWhen(exceptionDetected || redoRequired) + rspBuffer.output.ready := join.fire + output << join.haltWhen(exceptionDetected) if(memoryTranslatorPortConfig != null){ - redoRequired setWhen( stages.last.input.valid && mmu.joinCtx.refilling) - redoBranch.valid := redoRequired && iBusRsp.readyForError - redoBranch.payload := decode.input(PC) - - decode.arbitration.flushIt setWhen(redoBranch.valid) - decode.arbitration.flushNext setWhen(redoBranch.valid) + when(stages.last.input.valid && mmu.joinCtx.refilling) { + iBusRsp.redoFetch := True + } } diff --git a/src/main/scala/vexriscv/plugin/Misc.scala b/src/main/scala/vexriscv/plugin/Misc.scala index 8f68e4e..60c1682 100644 --- a/src/main/scala/vexriscv/plugin/Misc.scala +++ b/src/main/scala/vexriscv/plugin/Misc.scala @@ -122,7 +122,7 @@ object StreamForkVex{ object StreamVexPimper{ implicit class StreamFlushPimper[T <: Data](pimped : Stream[T]){ - def m2sPipeWithFlush(flush : Bool, discardInput : Boolean = true, collapsBubble : Boolean = true): Stream[T] = { + def m2sPipeWithFlush(flush : Bool, discardInput : Boolean = true, collapsBubble : Boolean = true, flushInput : Bool = null): Stream[T] = { val ret = cloneOf(pimped) val rValid = RegInit(False) @@ -132,7 +132,10 @@ object StreamVexPimper{ pimped.ready := (Bool(collapsBubble) && !ret.valid) || ret.ready when(pimped.ready) { - rValid := pimped.valid + if(flushInput == null) + rValid := pimped.valid + else + rValid := pimped.valid && !flushInput rData := pimped.payload } diff --git a/src/main/scala/vexriscv/plugin/MulPlugin.scala b/src/main/scala/vexriscv/plugin/MulPlugin.scala index 96db3e9..31714e8 100644 --- a/src/main/scala/vexriscv/plugin/MulPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulPlugin.scala @@ -2,6 +2,7 @@ package vexriscv.plugin import vexriscv._ import vexriscv.VexRiscv import spinal.core._ +import spinal.lib.KeepAttribute //Input buffer generaly avoid the FPGA synthesis to duplicate reg inside the DSP cell, which could stress timings quite much. class MulPlugin(inputBuffer : Boolean = false) extends Plugin[VexRiscv]{ @@ -94,6 +95,12 @@ class MulPlugin(inputBuffer : Boolean = false) extends Plugin[VexRiscv]{ insert(MUL_LH) := aSLow * bHigh insert(MUL_HL) := aHigh * bSLow insert(MUL_HH) := aHigh * bHigh + + Component.current.afterElaboration{ + //Avoid synthesis tools to retime RS1 RS2 from execute stage to decode stage leading to bad timings (ex : Vivado, even if retiming is disabled) + KeepAttribute(input(RS1)) + KeepAttribute(input(RS2)) + } } //First aggregation of partial multiplication diff --git a/src/test/cpp/raw/deleg/build/deleg.asm b/src/test/cpp/raw/deleg/build/deleg.asm index 9e3098f..e64c374 100644 --- a/src/test/cpp/raw/deleg/build/deleg.asm +++ b/src/test/cpp/raw/deleg/build/deleg.asm @@ -6,536 +6,744 @@ Disassembly of section .crt_section: 80000000 <_start>: 80000000: 00100e93 li t4,1 -80000004: 00000097 auipc ra,0x0 -80000008: 6fc08093 addi ra,ra,1788 # 80000700 +80000004: 00001097 auipc ra,0x1 +80000008: a3c08093 addi ra,ra,-1476 # 80000a40 8000000c: 30509073 csrw mtvec,ra -80000010: 00000097 auipc ra,0x0 -80000014: 72808093 addi ra,ra,1832 # 80000738 +80000010: 00001097 auipc ra,0x1 +80000014: a6808093 addi ra,ra,-1432 # 80000a78 80000018: 10509073 csrw stvec,ra 8000001c: f00110b7 lui ra,0xf0011 80000020: 00000113 li sp,0 -80000024: 0020a023 sw sp,0(ra) # f0011000 +80000024: 0020a023 sw sp,0(ra) # f0011000 +80000028: 00000013 nop +8000002c: 00000013 nop +80000030: 00000013 nop +80000034: 00000013 nop +80000038: 00000013 nop +8000003c: 00000013 nop +80000040: 00000013 nop +80000044: 00000013 nop -80000028 : -80000028: 00100e13 li t3,1 -8000002c: 00000f17 auipc t5,0x0 -80000030: 00cf0f13 addi t5,t5,12 # 80000038 -80000034: 00000073 ecall +80000048 : +80000048: 00100e13 li t3,1 +8000004c: 00000f17 auipc t5,0x0 +80000050: 00cf0f13 addi t5,t5,12 # 80000058 +80000054: 00000073 ecall -80000038 : -80000038: 00200e13 li t3,2 -8000003c: 000020b7 lui ra,0x2 -80000040: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -80000044: 00000113 li sp,0 -80000048: 3000b073 csrc mstatus,ra -8000004c: 30012073 csrs mstatus,sp -80000050: 00000097 auipc ra,0x0 -80000054: 01408093 addi ra,ra,20 # 80000064 -80000058: 34109073 csrw mepc,ra -8000005c: 30200073 mret -80000060: 6880006f j 800006e8 -80000064: 00000f17 auipc t5,0x0 -80000068: 024f0f13 addi t5,t5,36 # 80000088 -8000006c: 00000073 ecall -80000070: 6780006f j 800006e8 +80000058 : +80000058: 00200e13 li t3,2 +8000005c: 000020b7 lui ra,0x2 +80000060: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000064: 00000113 li sp,0 +80000068: 3000b073 csrc mstatus,ra +8000006c: 30012073 csrs mstatus,sp +80000070: 00000097 auipc ra,0x0 +80000074: 01408093 addi ra,ra,20 # 80000084 +80000078: 34109073 csrw mepc,ra +8000007c: 30200073 mret +80000080: 1a90006f j 80000a28 +80000084: 00000f17 auipc t5,0x0 +80000088: 024f0f13 addi t5,t5,36 # 800000a8 +8000008c: 00000073 ecall +80000090: 1990006f j 80000a28 -80000074 : -80000074: 00300e13 li t3,3 -80000078: 00000f17 auipc t5,0x0 -8000007c: 010f0f13 addi t5,t5,16 # 80000088 -80000080: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> -80000084: 6640006f j 800006e8 +80000094 : +80000094: 00300e13 li t3,3 +80000098: 00000f17 auipc t5,0x0 +8000009c: 010f0f13 addi t5,t5,16 # 800000a8 +800000a0: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +800000a4: 1850006f j 80000a28 -80000088 : -80000088: 00400e13 li t3,4 -8000008c: 000020b7 lui ra,0x2 -80000090: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -80000094: 00001137 lui sp,0x1 -80000098: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> -8000009c: 3000b073 csrc mstatus,ra -800000a0: 30012073 csrs mstatus,sp -800000a4: 00000097 auipc ra,0x0 -800000a8: 01408093 addi ra,ra,20 # 800000b8 -800000ac: 34109073 csrw mepc,ra -800000b0: 30200073 mret -800000b4: 6340006f j 800006e8 -800000b8: 00000f17 auipc t5,0x0 -800000bc: 010f0f13 addi t5,t5,16 # 800000c8 -800000c0: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> -800000c4: 6240006f j 800006e8 +800000a8 : +800000a8: 00400e13 li t3,4 +800000ac: 000020b7 lui ra,0x2 +800000b0: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +800000b4: 00001137 lui sp,0x1 +800000b8: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +800000bc: 3000b073 csrc mstatus,ra +800000c0: 30012073 csrs mstatus,sp +800000c4: 00000097 auipc ra,0x0 +800000c8: 01408093 addi ra,ra,20 # 800000d8 +800000cc: 34109073 csrw mepc,ra +800000d0: 30200073 mret +800000d4: 1550006f j 80000a28 +800000d8: 00000f17 auipc t5,0x0 +800000dc: 010f0f13 addi t5,t5,16 # 800000e8 +800000e0: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +800000e4: 1450006f j 80000a28 -800000c8 : -800000c8: 00500e13 li t3,5 -800000cc: 000020b7 lui ra,0x2 -800000d0: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -800000d4: 00000113 li sp,0 -800000d8: 3000b073 csrc mstatus,ra -800000dc: 30012073 csrs mstatus,sp -800000e0: 00000097 auipc ra,0x0 -800000e4: 01408093 addi ra,ra,20 # 800000f4 -800000e8: 34109073 csrw mepc,ra -800000ec: 30200073 mret -800000f0: 5f80006f j 800006e8 -800000f4: 00000f17 auipc t5,0x0 -800000f8: 010f0f13 addi t5,t5,16 # 80000104 -800000fc: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> -80000100: 5e80006f j 800006e8 - -80000104 : -80000104: 00600e13 li t3,6 -80000108: 01000093 li ra,16 -8000010c: 30209073 csrw medeleg,ra - -80000110 : -80000110: 00700e13 li t3,7 +800000e8 : +800000e8: 00500e13 li t3,5 +800000ec: 000020b7 lui ra,0x2 +800000f0: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +800000f4: 00000113 li sp,0 +800000f8: 3000b073 csrc mstatus,ra +800000fc: 30012073 csrs mstatus,sp +80000100: 00000097 auipc ra,0x0 +80000104: 01408093 addi ra,ra,20 # 80000114 +80000108: 34109073 csrw mepc,ra +8000010c: 30200073 mret +80000110: 1190006f j 80000a28 80000114: 00000f17 auipc t5,0x0 -80000118: 010f0f13 addi t5,t5,16 # 80000124 +80000118: 010f0f13 addi t5,t5,16 # 80000124 8000011c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> -80000120: 5c80006f j 800006e8 +80000120: 1090006f j 80000a28 -80000124 : -80000124: 00800e13 li t3,8 -80000128: 00000f17 auipc t5,0x0 -8000012c: 03cf0f13 addi t5,t5,60 # 80000164 -80000130: 000020b7 lui ra,0x2 -80000134: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -80000138: 00001137 lui sp,0x1 -8000013c: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> -80000140: 3000b073 csrc mstatus,ra -80000144: 30012073 csrs mstatus,sp -80000148: 00000097 auipc ra,0x0 -8000014c: 01408093 addi ra,ra,20 # 8000015c -80000150: 34109073 csrw mepc,ra -80000154: 30200073 mret -80000158: 5900006f j 800006e8 -8000015c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> -80000160: 5880006f j 800006e8 +80000124 : +80000124: 00600e13 li t3,6 +80000128: 01000093 li ra,16 +8000012c: 30209073 csrw medeleg,ra -80000164 : -80000164: 00900e13 li t3,9 -80000168: 00000f17 auipc t5,0x0 -8000016c: 038f0f13 addi t5,t5,56 # 800001a0 -80000170: 000020b7 lui ra,0x2 -80000174: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -80000178: 00000113 li sp,0 -8000017c: 3000b073 csrc mstatus,ra -80000180: 30012073 csrs mstatus,sp -80000184: 00000097 auipc ra,0x0 -80000188: 01408093 addi ra,ra,20 # 80000198 -8000018c: 34109073 csrw mepc,ra -80000190: 30200073 mret -80000194: 5540006f j 800006e8 -80000198: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> -8000019c: 54c0006f j 800006e8 +80000130 : +80000130: 00700e13 li t3,7 +80000134: 00000f17 auipc t5,0x0 +80000138: 010f0f13 addi t5,t5,16 # 80000144 +8000013c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +80000140: 0e90006f j 80000a28 -800001a0 : -800001a0: 00a00e13 li t3,10 -800001a4: 00000f17 auipc t5,0x0 -800001a8: 03cf0f13 addi t5,t5,60 # 800001e0 -800001ac: f00110b7 lui ra,0xf0011 -800001b0: 00000113 li sp,0 -800001b4: 0020a023 sw sp,0(ra) # f0011000 -800001b8: 00800093 li ra,8 -800001bc: 30009073 csrw mstatus,ra -800001c0: 000010b7 lui ra,0x1 -800001c4: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800> -800001c8: 30409073 csrw mie,ra +80000144 : +80000144: 00800e13 li t3,8 +80000148: 00000f17 auipc t5,0x0 +8000014c: 03cf0f13 addi t5,t5,60 # 80000184 +80000150: 000020b7 lui ra,0x2 +80000154: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000158: 00001137 lui sp,0x1 +8000015c: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +80000160: 3000b073 csrc mstatus,ra +80000164: 30012073 csrs mstatus,sp +80000168: 00000097 auipc ra,0x0 +8000016c: 01408093 addi ra,ra,20 # 8000017c +80000170: 34109073 csrw mepc,ra +80000174: 30200073 mret +80000178: 0b10006f j 80000a28 +8000017c: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +80000180: 0a90006f j 80000a28 + +80000184 : +80000184: 00900e13 li t3,9 +80000188: 00000f17 auipc t5,0x0 +8000018c: 038f0f13 addi t5,t5,56 # 800001c0 +80000190: 000020b7 lui ra,0x2 +80000194: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000198: 00000113 li sp,0 +8000019c: 3000b073 csrc mstatus,ra +800001a0: 30012073 csrs mstatus,sp +800001a4: 00000097 auipc ra,0x0 +800001a8: 01408093 addi ra,ra,20 # 800001b8 +800001ac: 34109073 csrw mepc,ra +800001b0: 30200073 mret +800001b4: 0750006f j 80000a28 +800001b8: 00102083 lw ra,1(zero) # 1 <_start-0x7fffffff> +800001bc: 06d0006f j 80000a28 + +800001c0 : +800001c0: 00a00e13 li t3,10 +800001c4: 00000f17 auipc t5,0x0 +800001c8: 07cf0f13 addi t5,t5,124 # 80000240 800001cc: f00110b7 lui ra,0xf0011 -800001d0: 00100113 li sp,1 -800001d4: 0020a023 sw sp,0(ra) # f0011000 -800001d8: 10500073 wfi -800001dc: 50c0006f j 800006e8 - -800001e0 : -800001e0: 00b00e13 li t3,11 -800001e4: 00000f17 auipc t5,0x0 -800001e8: 068f0f13 addi t5,t5,104 # 8000024c -800001ec: f00110b7 lui ra,0xf0011 -800001f0: 00000113 li sp,0 -800001f4: 0020a023 sw sp,0(ra) # f0011000 +800001d0: 00000113 li sp,0 +800001d4: 0020a023 sw sp,0(ra) # f0011000 +800001d8: 00000013 nop +800001dc: 00000013 nop +800001e0: 00000013 nop +800001e4: 00000013 nop +800001e8: 00000013 nop +800001ec: 00000013 nop +800001f0: 00000013 nop +800001f4: 00000013 nop 800001f8: 00800093 li ra,8 800001fc: 30009073 csrw mstatus,ra 80000200: 000010b7 lui ra,0x1 80000204: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800> 80000208: 30409073 csrw mie,ra -8000020c: 000020b7 lui ra,0x2 -80000210: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -80000214: 00001137 lui sp,0x1 -80000218: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> -8000021c: 3000b073 csrc mstatus,ra -80000220: 30012073 csrs mstatus,sp -80000224: 00000097 auipc ra,0x0 -80000228: 01408093 addi ra,ra,20 # 80000238 -8000022c: 34109073 csrw mepc,ra -80000230: 30200073 mret -80000234: 4b40006f j 800006e8 -80000238: f00110b7 lui ra,0xf0011 -8000023c: 00100113 li sp,1 -80000240: 0020a023 sw sp,0(ra) # f0011000 -80000244: 10500073 wfi -80000248: 4a00006f j 800006e8 +8000020c: f00110b7 lui ra,0xf0011 +80000210: 00100113 li sp,1 +80000214: 0020a023 sw sp,0(ra) # f0011000 +80000218: 00000013 nop +8000021c: 00000013 nop +80000220: 00000013 nop +80000224: 00000013 nop +80000228: 00000013 nop +8000022c: 00000013 nop +80000230: 00000013 nop +80000234: 00000013 nop +80000238: 10500073 wfi +8000023c: 7ec0006f j 80000a28 -8000024c : -8000024c: 00c00e13 li t3,12 -80000250: 00000f17 auipc t5,0x0 -80000254: 064f0f13 addi t5,t5,100 # 800002b4 -80000258: f00110b7 lui ra,0xf0011 -8000025c: 00000113 li sp,0 -80000260: 0020a023 sw sp,0(ra) # f0011000 -80000264: 00800093 li ra,8 -80000268: 30009073 csrw mstatus,ra -8000026c: 000010b7 lui ra,0x1 -80000270: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800> -80000274: 30409073 csrw mie,ra -80000278: 000020b7 lui ra,0x2 -8000027c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -80000280: 00000113 li sp,0 -80000284: 3000b073 csrc mstatus,ra -80000288: 30012073 csrs mstatus,sp -8000028c: 00000097 auipc ra,0x0 -80000290: 01408093 addi ra,ra,20 # 800002a0 -80000294: 34109073 csrw mepc,ra -80000298: 30200073 mret -8000029c: 44c0006f j 800006e8 -800002a0: f00110b7 lui ra,0xf0011 -800002a4: 00100113 li sp,1 -800002a8: 0020a023 sw sp,0(ra) # f0011000 -800002ac: 10500073 wfi -800002b0: 4380006f j 800006e8 +80000240 : +80000240: 00b00e13 li t3,11 +80000244: 00000f17 auipc t5,0x0 +80000248: 0a8f0f13 addi t5,t5,168 # 800002ec +8000024c: f00110b7 lui ra,0xf0011 +80000250: 00000113 li sp,0 +80000254: 0020a023 sw sp,0(ra) # f0011000 +80000258: 00000013 nop +8000025c: 00000013 nop +80000260: 00000013 nop +80000264: 00000013 nop +80000268: 00000013 nop +8000026c: 00000013 nop +80000270: 00000013 nop +80000274: 00000013 nop +80000278: 00800093 li ra,8 +8000027c: 30009073 csrw mstatus,ra +80000280: 000010b7 lui ra,0x1 +80000284: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800> +80000288: 30409073 csrw mie,ra +8000028c: 000020b7 lui ra,0x2 +80000290: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000294: 00001137 lui sp,0x1 +80000298: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +8000029c: 3000b073 csrc mstatus,ra +800002a0: 30012073 csrs mstatus,sp +800002a4: 00000097 auipc ra,0x0 +800002a8: 01408093 addi ra,ra,20 # 800002b8 +800002ac: 34109073 csrw mepc,ra +800002b0: 30200073 mret +800002b4: 7740006f j 80000a28 +800002b8: f00110b7 lui ra,0xf0011 +800002bc: 00100113 li sp,1 +800002c0: 0020a023 sw sp,0(ra) # f0011000 +800002c4: 00000013 nop +800002c8: 00000013 nop +800002cc: 00000013 nop +800002d0: 00000013 nop +800002d4: 00000013 nop +800002d8: 00000013 nop +800002dc: 00000013 nop +800002e0: 00000013 nop +800002e4: 10500073 wfi +800002e8: 7400006f j 80000a28 -800002b4 : -800002b4: 00200093 li ra,2 -800002b8: 10009073 csrw sstatus,ra -800002bc: 00e00e13 li t3,14 -800002c0: 00000f17 auipc t5,0x0 -800002c4: 040f0f13 addi t5,t5,64 # 80000300 -800002c8: f00120b7 lui ra,0xf0012 -800002cc: 00000113 li sp,0 -800002d0: 0020a023 sw sp,0(ra) # f0012000 -800002d4: 00200093 li ra,2 -800002d8: 30009073 csrw mstatus,ra -800002dc: 20000093 li ra,512 -800002e0: 30409073 csrw mie,ra -800002e4: 00000e93 li t4,0 -800002e8: f00120b7 lui ra,0xf0012 -800002ec: 00100113 li sp,1 -800002f0: 0020a023 sw sp,0(ra) # f0012000 -800002f4: 06400093 li ra,100 -800002f8: fff08093 addi ra,ra,-1 -800002fc: fe104ee3 bgtz ra,800002f8 +800002ec : +800002ec: 00c00e13 li t3,12 +800002f0: 00000f17 auipc t5,0x0 +800002f4: 0a4f0f13 addi t5,t5,164 # 80000394 +800002f8: f00110b7 lui ra,0xf0011 +800002fc: 00000113 li sp,0 +80000300: 0020a023 sw sp,0(ra) # f0011000 +80000304: 00000013 nop +80000308: 00000013 nop +8000030c: 00000013 nop +80000310: 00000013 nop +80000314: 00000013 nop +80000318: 00000013 nop +8000031c: 00000013 nop +80000320: 00000013 nop +80000324: 00800093 li ra,8 +80000328: 30009073 csrw mstatus,ra +8000032c: 000010b7 lui ra,0x1 +80000330: 80008093 addi ra,ra,-2048 # 800 <_start-0x7ffff800> +80000334: 30409073 csrw mie,ra +80000338: 000020b7 lui ra,0x2 +8000033c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000340: 00000113 li sp,0 +80000344: 3000b073 csrc mstatus,ra +80000348: 30012073 csrs mstatus,sp +8000034c: 00000097 auipc ra,0x0 +80000350: 01408093 addi ra,ra,20 # 80000360 +80000354: 34109073 csrw mepc,ra +80000358: 30200073 mret +8000035c: 6cc0006f j 80000a28 +80000360: f00110b7 lui ra,0xf0011 +80000364: 00100113 li sp,1 +80000368: 0020a023 sw sp,0(ra) # f0011000 +8000036c: 00000013 nop +80000370: 00000013 nop +80000374: 00000013 nop +80000378: 00000013 nop +8000037c: 00000013 nop +80000380: 00000013 nop +80000384: 00000013 nop +80000388: 00000013 nop +8000038c: 10500073 wfi +80000390: 6980006f j 80000a28 -80000300 : -80000300: 00f00e13 li t3,15 -80000304: 00000f17 auipc t5,0x0 -80000308: 068f0f13 addi t5,t5,104 # 8000036c -8000030c: f00120b7 lui ra,0xf0012 -80000310: 00000113 li sp,0 -80000314: 0020a023 sw sp,0(ra) # f0012000 -80000318: 00200093 li ra,2 -8000031c: 30009073 csrw mstatus,ra -80000320: 20000093 li ra,512 -80000324: 30409073 csrw mie,ra -80000328: 000020b7 lui ra,0x2 -8000032c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -80000330: 00001137 lui sp,0x1 -80000334: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> -80000338: 3000b073 csrc mstatus,ra -8000033c: 30012073 csrs mstatus,sp -80000340: 00000097 auipc ra,0x0 -80000344: 01408093 addi ra,ra,20 # 80000354 -80000348: 34109073 csrw mepc,ra -8000034c: 30200073 mret -80000350: 3980006f j 800006e8 -80000354: 00100e93 li t4,1 -80000358: f00120b7 lui ra,0xf0012 -8000035c: 00100113 li sp,1 -80000360: 0020a023 sw sp,0(ra) # f0012000 -80000364: 10500073 wfi -80000368: 3800006f j 800006e8 +80000394 : +80000394: 00200093 li ra,2 +80000398: 10009073 csrw sstatus,ra +8000039c: 00e00e13 li t3,14 +800003a0: 00000f17 auipc t5,0x0 +800003a4: 080f0f13 addi t5,t5,128 # 80000420 +800003a8: f00120b7 lui ra,0xf0012 +800003ac: 00000113 li sp,0 +800003b0: 0020a023 sw sp,0(ra) # f0012000 +800003b4: 00000013 nop +800003b8: 00000013 nop +800003bc: 00000013 nop +800003c0: 00000013 nop +800003c4: 00000013 nop +800003c8: 00000013 nop +800003cc: 00000013 nop +800003d0: 00000013 nop +800003d4: 00200093 li ra,2 +800003d8: 30009073 csrw mstatus,ra +800003dc: 20000093 li ra,512 +800003e0: 30409073 csrw mie,ra +800003e4: 00000e93 li t4,0 +800003e8: f00120b7 lui ra,0xf0012 +800003ec: 00100113 li sp,1 +800003f0: 0020a023 sw sp,0(ra) # f0012000 +800003f4: 00000013 nop +800003f8: 00000013 nop +800003fc: 00000013 nop +80000400: 00000013 nop +80000404: 00000013 nop +80000408: 00000013 nop +8000040c: 00000013 nop +80000410: 00000013 nop +80000414: 06400093 li ra,100 +80000418: fff08093 addi ra,ra,-1 +8000041c: fe104ee3 bgtz ra,80000418 -8000036c : -8000036c: 01000e13 li t3,16 -80000370: 00000f17 auipc t5,0x0 -80000374: 060f0f13 addi t5,t5,96 # 800003d0 -80000378: f00120b7 lui ra,0xf0012 -8000037c: 00000113 li sp,0 -80000380: 0020a023 sw sp,0(ra) # f0012000 -80000384: 00200093 li ra,2 -80000388: 30009073 csrw mstatus,ra -8000038c: 20000093 li ra,512 -80000390: 30409073 csrw mie,ra -80000394: 000020b7 lui ra,0x2 -80000398: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -8000039c: 00000113 li sp,0 -800003a0: 3000b073 csrc mstatus,ra -800003a4: 30012073 csrs mstatus,sp -800003a8: 00000097 auipc ra,0x0 -800003ac: 01408093 addi ra,ra,20 # 800003bc -800003b0: 34109073 csrw mepc,ra -800003b4: 30200073 mret -800003b8: 3300006f j 800006e8 -800003bc: f00120b7 lui ra,0xf0012 -800003c0: 00100113 li sp,1 -800003c4: 0020a023 sw sp,0(ra) # f0012000 -800003c8: 10500073 wfi -800003cc: 31c0006f j 800006e8 +80000420 : +80000420: 00f00e13 li t3,15 +80000424: 00000f17 auipc t5,0x0 +80000428: 0a8f0f13 addi t5,t5,168 # 800004cc +8000042c: f00120b7 lui ra,0xf0012 +80000430: 00000113 li sp,0 +80000434: 0020a023 sw sp,0(ra) # f0012000 +80000438: 00000013 nop +8000043c: 00000013 nop +80000440: 00000013 nop +80000444: 00000013 nop +80000448: 00000013 nop +8000044c: 00000013 nop +80000450: 00000013 nop +80000454: 00000013 nop +80000458: 00200093 li ra,2 +8000045c: 30009073 csrw mstatus,ra +80000460: 20000093 li ra,512 +80000464: 30409073 csrw mie,ra +80000468: 000020b7 lui ra,0x2 +8000046c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000470: 00001137 lui sp,0x1 +80000474: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +80000478: 3000b073 csrc mstatus,ra +8000047c: 30012073 csrs mstatus,sp +80000480: 00000097 auipc ra,0x0 +80000484: 01408093 addi ra,ra,20 # 80000494 +80000488: 34109073 csrw mepc,ra +8000048c: 30200073 mret +80000490: 5980006f j 80000a28 +80000494: 00100e93 li t4,1 +80000498: f00120b7 lui ra,0xf0012 +8000049c: 00100113 li sp,1 +800004a0: 0020a023 sw sp,0(ra) # f0012000 +800004a4: 00000013 nop +800004a8: 00000013 nop +800004ac: 00000013 nop +800004b0: 00000013 nop +800004b4: 00000013 nop +800004b8: 00000013 nop +800004bc: 00000013 nop +800004c0: 00000013 nop +800004c4: 10500073 wfi +800004c8: 5600006f j 80000a28 -800003d0 : -800003d0: 01100e13 li t3,17 -800003d4: 20000093 li ra,512 -800003d8: 30309073 csrw mideleg,ra -800003dc: 00000f17 auipc t5,0x0 -800003e0: 040f0f13 addi t5,t5,64 # 8000041c -800003e4: f00120b7 lui ra,0xf0012 -800003e8: 00000113 li sp,0 -800003ec: 0020a023 sw sp,0(ra) # f0012000 -800003f0: 00200093 li ra,2 -800003f4: 30009073 csrw mstatus,ra -800003f8: 20000093 li ra,512 -800003fc: 30409073 csrw mie,ra -80000400: 00000e93 li t4,0 -80000404: f00120b7 lui ra,0xf0012 -80000408: 00100113 li sp,1 -8000040c: 0020a023 sw sp,0(ra) # f0012000 -80000410: 06400093 li ra,100 -80000414: fff08093 addi ra,ra,-1 -80000418: fe104ee3 bgtz ra,80000414 - -8000041c : -8000041c: 01200e13 li t3,18 -80000420: 00000f17 auipc t5,0x0 -80000424: 068f0f13 addi t5,t5,104 # 80000488 -80000428: f00120b7 lui ra,0xf0012 -8000042c: 00000113 li sp,0 -80000430: 0020a023 sw sp,0(ra) # f0012000 -80000434: 00200093 li ra,2 -80000438: 30009073 csrw mstatus,ra -8000043c: 20000093 li ra,512 -80000440: 30409073 csrw mie,ra -80000444: 000020b7 lui ra,0x2 -80000448: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -8000044c: 00001137 lui sp,0x1 -80000450: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> -80000454: 3000b073 csrc mstatus,ra -80000458: 30012073 csrs mstatus,sp -8000045c: 00000097 auipc ra,0x0 -80000460: 01408093 addi ra,ra,20 # 80000470 -80000464: 34109073 csrw mepc,ra -80000468: 30200073 mret -8000046c: 27c0006f j 800006e8 -80000470: 00100e93 li t4,1 -80000474: f00120b7 lui ra,0xf0012 -80000478: 00100113 li sp,1 -8000047c: 0020a023 sw sp,0(ra) # f0012000 -80000480: 10500073 wfi -80000484: 2640006f j 800006e8 - -80000488 : -80000488: 01300e13 li t3,19 -8000048c: 00000f17 auipc t5,0x0 -80000490: 060f0f13 addi t5,t5,96 # 800004ec -80000494: f00120b7 lui ra,0xf0012 -80000498: 00000113 li sp,0 -8000049c: 0020a023 sw sp,0(ra) # f0012000 -800004a0: 00200093 li ra,2 -800004a4: 30009073 csrw mstatus,ra -800004a8: 20000093 li ra,512 -800004ac: 30409073 csrw mie,ra -800004b0: 000020b7 lui ra,0x2 -800004b4: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -800004b8: 00000113 li sp,0 -800004bc: 3000b073 csrc mstatus,ra -800004c0: 30012073 csrs mstatus,sp -800004c4: 00000097 auipc ra,0x0 -800004c8: 01408093 addi ra,ra,20 # 800004d8 -800004cc: 34109073 csrw mepc,ra -800004d0: 30200073 mret -800004d4: 2140006f j 800006e8 +800004cc : +800004cc: 01000e13 li t3,16 +800004d0: 00000f17 auipc t5,0x0 +800004d4: 0a0f0f13 addi t5,t5,160 # 80000570 800004d8: f00120b7 lui ra,0xf0012 -800004dc: 00100113 li sp,1 -800004e0: 0020a023 sw sp,0(ra) # f0012000 -800004e4: 10500073 wfi -800004e8: 2000006f j 800006e8 - -800004ec : -800004ec: f00120b7 lui ra,0xf0012 -800004f0: 00000113 li sp,0 -800004f4: 0020a023 sw sp,0(ra) # f0012000 -800004f8: 01400e13 li t3,20 -800004fc: 00000f17 auipc t5,0x0 -80000500: 030f0f13 addi t5,t5,48 # 8000052c +800004dc: 00000113 li sp,0 +800004e0: 0020a023 sw sp,0(ra) # f0012000 +800004e4: 00000013 nop +800004e8: 00000013 nop +800004ec: 00000013 nop +800004f0: 00000013 nop +800004f4: 00000013 nop +800004f8: 00000013 nop +800004fc: 00000013 nop +80000500: 00000013 nop 80000504: 00200093 li ra,2 80000508: 30009073 csrw mstatus,ra 8000050c: 20000093 li ra,512 80000510: 30409073 csrw mie,ra -80000514: 00000e93 li t4,0 -80000518: 20000093 li ra,512 -8000051c: 1440a073 csrs sip,ra -80000520: 06400093 li ra,100 -80000524: fff08093 addi ra,ra,-1 -80000528: fe104ee3 bgtz ra,80000524 +80000514: 000020b7 lui ra,0x2 +80000518: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +8000051c: 00000113 li sp,0 +80000520: 3000b073 csrc mstatus,ra +80000524: 30012073 csrs mstatus,sp +80000528: 00000097 auipc ra,0x0 +8000052c: 01408093 addi ra,ra,20 # 8000053c +80000530: 34109073 csrw mepc,ra +80000534: 30200073 mret +80000538: 4f00006f j 80000a28 +8000053c: f00120b7 lui ra,0xf0012 +80000540: 00100113 li sp,1 +80000544: 0020a023 sw sp,0(ra) # f0012000 +80000548: 00000013 nop +8000054c: 00000013 nop +80000550: 00000013 nop +80000554: 00000013 nop +80000558: 00000013 nop +8000055c: 00000013 nop +80000560: 00000013 nop +80000564: 00000013 nop +80000568: 10500073 wfi +8000056c: 4bc0006f j 80000a28 -8000052c : -8000052c: 01500e13 li t3,21 -80000530: 00000f17 auipc t5,0x0 -80000534: 060f0f13 addi t5,t5,96 # 80000590 -80000538: 20000093 li ra,512 -8000053c: 1440b073 csrc sip,ra -80000540: 00200093 li ra,2 -80000544: 30009073 csrw mstatus,ra -80000548: 20000093 li ra,512 -8000054c: 30409073 csrw mie,ra -80000550: 000020b7 lui ra,0x2 -80000554: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -80000558: 00001137 lui sp,0x1 -8000055c: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> -80000560: 3000b073 csrc mstatus,ra -80000564: 30012073 csrs mstatus,sp -80000568: 00000097 auipc ra,0x0 -8000056c: 01408093 addi ra,ra,20 # 8000057c -80000570: 34109073 csrw mepc,ra -80000574: 30200073 mret -80000578: 1700006f j 800006e8 -8000057c: 00100e93 li t4,1 -80000580: 20000093 li ra,512 -80000584: 1440a073 csrs sip,ra -80000588: 10500073 wfi -8000058c: 15c0006f j 800006e8 +80000570 : +80000570: 01100e13 li t3,17 +80000574: 20000093 li ra,512 +80000578: 30309073 csrw mideleg,ra +8000057c: 00000f17 auipc t5,0x0 +80000580: 080f0f13 addi t5,t5,128 # 800005fc +80000584: f00120b7 lui ra,0xf0012 +80000588: 00000113 li sp,0 +8000058c: 0020a023 sw sp,0(ra) # f0012000 +80000590: 00000013 nop +80000594: 00000013 nop +80000598: 00000013 nop +8000059c: 00000013 nop +800005a0: 00000013 nop +800005a4: 00000013 nop +800005a8: 00000013 nop +800005ac: 00000013 nop +800005b0: 00200093 li ra,2 +800005b4: 30009073 csrw mstatus,ra +800005b8: 20000093 li ra,512 +800005bc: 30409073 csrw mie,ra +800005c0: 00000e93 li t4,0 +800005c4: f00120b7 lui ra,0xf0012 +800005c8: 00100113 li sp,1 +800005cc: 0020a023 sw sp,0(ra) # f0012000 +800005d0: 00000013 nop +800005d4: 00000013 nop +800005d8: 00000013 nop +800005dc: 00000013 nop +800005e0: 00000013 nop +800005e4: 00000013 nop +800005e8: 00000013 nop +800005ec: 00000013 nop +800005f0: 06400093 li ra,100 +800005f4: fff08093 addi ra,ra,-1 +800005f8: fe104ee3 bgtz ra,800005f4 -80000590 : -80000590: 01600e13 li t3,22 -80000594: 00000f17 auipc t5,0x0 -80000598: 058f0f13 addi t5,t5,88 # 800005ec -8000059c: 20000093 li ra,512 -800005a0: 1440b073 csrc sip,ra -800005a4: 00200093 li ra,2 -800005a8: 30009073 csrw mstatus,ra -800005ac: 20000093 li ra,512 -800005b0: 30409073 csrw mie,ra -800005b4: 20000093 li ra,512 -800005b8: 1440a073 csrs sip,ra -800005bc: 000020b7 lui ra,0x2 -800005c0: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -800005c4: 00000113 li sp,0 -800005c8: 3000b073 csrc mstatus,ra -800005cc: 30012073 csrs mstatus,sp -800005d0: 00000097 auipc ra,0x0 -800005d4: 01408093 addi ra,ra,20 # 800005e4 -800005d8: 34109073 csrw mepc,ra -800005dc: 30200073 mret -800005e0: 1080006f j 800006e8 -800005e4: 10500073 wfi -800005e8: 1000006f j 800006e8 +800005fc : +800005fc: 01200e13 li t3,18 +80000600: 00000f17 auipc t5,0x0 +80000604: 0a8f0f13 addi t5,t5,168 # 800006a8 +80000608: f00120b7 lui ra,0xf0012 +8000060c: 00000113 li sp,0 +80000610: 0020a023 sw sp,0(ra) # f0012000 +80000614: 00000013 nop +80000618: 00000013 nop +8000061c: 00000013 nop +80000620: 00000013 nop +80000624: 00000013 nop +80000628: 00000013 nop +8000062c: 00000013 nop +80000630: 00000013 nop +80000634: 00200093 li ra,2 +80000638: 30009073 csrw mstatus,ra +8000063c: 20000093 li ra,512 +80000640: 30409073 csrw mie,ra +80000644: 000020b7 lui ra,0x2 +80000648: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +8000064c: 00001137 lui sp,0x1 +80000650: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +80000654: 3000b073 csrc mstatus,ra +80000658: 30012073 csrs mstatus,sp +8000065c: 00000097 auipc ra,0x0 +80000660: 01408093 addi ra,ra,20 # 80000670 +80000664: 34109073 csrw mepc,ra +80000668: 30200073 mret +8000066c: 3bc0006f j 80000a28 +80000670: 00100e93 li t4,1 +80000674: f00120b7 lui ra,0xf0012 +80000678: 00100113 li sp,1 +8000067c: 0020a023 sw sp,0(ra) # f0012000 +80000680: 00000013 nop +80000684: 00000013 nop +80000688: 00000013 nop +8000068c: 00000013 nop +80000690: 00000013 nop +80000694: 00000013 nop +80000698: 00000013 nop +8000069c: 00000013 nop +800006a0: 10500073 wfi +800006a4: 3840006f j 80000a28 -800005ec : -800005ec: 01700e13 li t3,23 -800005f0: 00000e93 li t4,0 -800005f4: f00120b7 lui ra,0xf0012 -800005f8: 00000113 li sp,0 -800005fc: 0020a023 sw sp,0(ra) # f0012000 -80000600: 20000093 li ra,512 -80000604: 1440b073 csrc sip,ra -80000608: 344021f3 csrr gp,mip -8000060c: f00120b7 lui ra,0xf0012 -80000610: 00100113 li sp,1 -80000614: 0020a023 sw sp,0(ra) # f0012000 -80000618: 20000093 li ra,512 -8000061c: 1440b073 csrc sip,ra -80000620: 344021f3 csrr gp,mip -80000624: f00120b7 lui ra,0xf0012 -80000628: 00000113 li sp,0 -8000062c: 0020a023 sw sp,0(ra) # f0012000 -80000630: 20000093 li ra,512 -80000634: 1440b073 csrc sip,ra -80000638: 344021f3 csrr gp,mip -8000063c: f00120b7 lui ra,0xf0012 -80000640: 00000113 li sp,0 -80000644: 0020a023 sw sp,0(ra) # f0012000 -80000648: 20000093 li ra,512 -8000064c: 1440a073 csrs sip,ra -80000650: 344021f3 csrr gp,mip -80000654: f00120b7 lui ra,0xf0012 -80000658: 00100113 li sp,1 -8000065c: 0020a023 sw sp,0(ra) # f0012000 -80000660: 20000093 li ra,512 -80000664: 1440a073 csrs sip,ra -80000668: 344021f3 csrr gp,mip -8000066c: f00120b7 lui ra,0xf0012 -80000670: 00000113 li sp,0 -80000674: 0020a023 sw sp,0(ra) # f0012000 +800006a8 : +800006a8: 01300e13 li t3,19 +800006ac: 00000f17 auipc t5,0x0 +800006b0: 0a0f0f13 addi t5,t5,160 # 8000074c +800006b4: f00120b7 lui ra,0xf0012 +800006b8: 00000113 li sp,0 +800006bc: 0020a023 sw sp,0(ra) # f0012000 +800006c0: 00000013 nop +800006c4: 00000013 nop +800006c8: 00000013 nop +800006cc: 00000013 nop +800006d0: 00000013 nop +800006d4: 00000013 nop +800006d8: 00000013 nop +800006dc: 00000013 nop +800006e0: 00200093 li ra,2 +800006e4: 30009073 csrw mstatus,ra +800006e8: 20000093 li ra,512 +800006ec: 30409073 csrw mie,ra +800006f0: 000020b7 lui ra,0x2 +800006f4: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +800006f8: 00000113 li sp,0 +800006fc: 3000b073 csrc mstatus,ra +80000700: 30012073 csrs mstatus,sp +80000704: 00000097 auipc ra,0x0 +80000708: 01408093 addi ra,ra,20 # 80000718 +8000070c: 34109073 csrw mepc,ra +80000710: 30200073 mret +80000714: 3140006f j 80000a28 +80000718: f00120b7 lui ra,0xf0012 +8000071c: 00100113 li sp,1 +80000720: 0020a023 sw sp,0(ra) # f0012000 +80000724: 00000013 nop +80000728: 00000013 nop +8000072c: 00000013 nop +80000730: 00000013 nop +80000734: 00000013 nop +80000738: 00000013 nop +8000073c: 00000013 nop +80000740: 00000013 nop +80000744: 10500073 wfi +80000748: 2e00006f j 80000a28 -80000678 : -80000678: 01800e13 li t3,24 -8000067c: 00200093 li ra,2 -80000680: 3040a073 csrs mie,ra -80000684: 3440a073 csrs mip,ra -80000688: 3000a073 csrs mstatus,ra -8000068c: 00100e93 li t4,1 -80000690: 00000f17 auipc t5,0x0 -80000694: 03cf0f13 addi t5,t5,60 # 800006cc -80000698: 000020b7 lui ra,0x2 -8000069c: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -800006a0: 00001137 lui sp,0x1 -800006a4: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> -800006a8: 3000b073 csrc mstatus,ra -800006ac: 30012073 csrs mstatus,sp -800006b0: 00000097 auipc ra,0x0 -800006b4: 01408093 addi ra,ra,20 # 800006c4 -800006b8: 34109073 csrw mepc,ra -800006bc: 30200073 mret -800006c0: 0280006f j 800006e8 - -800006c4 : -800006c4: 10500073 wfi -800006c8: 0200006f j 800006e8 - -800006cc : -800006cc: 01900e13 li t3,25 -800006d0: 00000f17 auipc t5,0x0 -800006d4: 014f0f13 addi t5,t5,20 # 800006e4 -800006d8: 30046073 csrsi mstatus,8 -800006dc: 10500073 wfi -800006e0: 0080006f j 800006e8 - -800006e4 : -800006e4: 0100006f j 800006f4 - -800006e8 : -800006e8: f0100137 lui sp,0xf0100 -800006ec: f2410113 addi sp,sp,-220 # f00fff24 -800006f0: 01c12023 sw t3,0(sp) - -800006f4 : -800006f4: f0100137 lui sp,0xf0100 -800006f8: f2010113 addi sp,sp,-224 # f00fff20 -800006fc: 00012023 sw zero,0(sp) - -80000700 : -80000700: fe0e84e3 beqz t4,800006e8 -80000704: 342020f3 csrr ra,mcause -80000708: 341020f3 csrr ra,mepc -8000070c: 300020f3 csrr ra,mstatus -80000710: 343020f3 csrr ra,mtval -80000714: 08000093 li ra,128 -80000718: 3000b073 csrc mstatus,ra -8000071c: 00200093 li ra,2 -80000720: fc1e8ae3 beq t4,ra,800006f4 -80000724: 000020b7 lui ra,0x2 -80000728: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> -8000072c: 3000a073 csrs mstatus,ra -80000730: 341f1073 csrw mepc,t5 -80000734: 30200073 mret - -80000738 : -80000738: fa0e88e3 beqz t4,800006e8 -8000073c: 142020f3 csrr ra,scause -80000740: 141020f3 csrr ra,sepc -80000744: 100020f3 csrr ra,sstatus -80000748: 143020f3 csrr ra,stval -8000074c: 00000073 ecall -80000750: 00000013 nop -80000754: 00000013 nop +8000074c : +8000074c: f00120b7 lui ra,0xf0012 +80000750: 00000113 li sp,0 +80000754: 0020a023 sw sp,0(ra) # f0012000 80000758: 00000013 nop 8000075c: 00000013 nop 80000760: 00000013 nop 80000764: 00000013 nop +80000768: 00000013 nop +8000076c: 00000013 nop +80000770: 00000013 nop +80000774: 00000013 nop +80000778: 01400e13 li t3,20 +8000077c: 00000f17 auipc t5,0x0 +80000780: 030f0f13 addi t5,t5,48 # 800007ac +80000784: 00200093 li ra,2 +80000788: 30009073 csrw mstatus,ra +8000078c: 20000093 li ra,512 +80000790: 30409073 csrw mie,ra +80000794: 00000e93 li t4,0 +80000798: 20000093 li ra,512 +8000079c: 1440a073 csrs sip,ra +800007a0: 06400093 li ra,100 +800007a4: fff08093 addi ra,ra,-1 +800007a8: fe104ee3 bgtz ra,800007a4 + +800007ac : +800007ac: 01500e13 li t3,21 +800007b0: 00000f17 auipc t5,0x0 +800007b4: 060f0f13 addi t5,t5,96 # 80000810 +800007b8: 20000093 li ra,512 +800007bc: 1440b073 csrc sip,ra +800007c0: 00200093 li ra,2 +800007c4: 30009073 csrw mstatus,ra +800007c8: 20000093 li ra,512 +800007cc: 30409073 csrw mie,ra +800007d0: 000020b7 lui ra,0x2 +800007d4: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +800007d8: 00001137 lui sp,0x1 +800007dc: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +800007e0: 3000b073 csrc mstatus,ra +800007e4: 30012073 csrs mstatus,sp +800007e8: 00000097 auipc ra,0x0 +800007ec: 01408093 addi ra,ra,20 # 800007fc +800007f0: 34109073 csrw mepc,ra +800007f4: 30200073 mret +800007f8: 2300006f j 80000a28 +800007fc: 00100e93 li t4,1 +80000800: 20000093 li ra,512 +80000804: 1440a073 csrs sip,ra +80000808: 10500073 wfi +8000080c: 21c0006f j 80000a28 + +80000810 : +80000810: 01600e13 li t3,22 +80000814: 00000f17 auipc t5,0x0 +80000818: 058f0f13 addi t5,t5,88 # 8000086c +8000081c: 20000093 li ra,512 +80000820: 1440b073 csrc sip,ra +80000824: 00200093 li ra,2 +80000828: 30009073 csrw mstatus,ra +8000082c: 20000093 li ra,512 +80000830: 30409073 csrw mie,ra +80000834: 20000093 li ra,512 +80000838: 1440a073 csrs sip,ra +8000083c: 000020b7 lui ra,0x2 +80000840: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000844: 00000113 li sp,0 +80000848: 3000b073 csrc mstatus,ra +8000084c: 30012073 csrs mstatus,sp +80000850: 00000097 auipc ra,0x0 +80000854: 01408093 addi ra,ra,20 # 80000864 +80000858: 34109073 csrw mepc,ra +8000085c: 30200073 mret +80000860: 1c80006f j 80000a28 +80000864: 10500073 wfi +80000868: 1c00006f j 80000a28 + +8000086c : +8000086c: 01700e13 li t3,23 +80000870: 00000e93 li t4,0 +80000874: f00120b7 lui ra,0xf0012 +80000878: 00000113 li sp,0 +8000087c: 0020a023 sw sp,0(ra) # f0012000 +80000880: 00000013 nop +80000884: 00000013 nop +80000888: 00000013 nop +8000088c: 00000013 nop +80000890: 00000013 nop +80000894: 00000013 nop +80000898: 00000013 nop +8000089c: 00000013 nop +800008a0: 20000093 li ra,512 +800008a4: 1440b073 csrc sip,ra +800008a8: 344021f3 csrr gp,mip +800008ac: f00120b7 lui ra,0xf0012 +800008b0: 00100113 li sp,1 +800008b4: 0020a023 sw sp,0(ra) # f0012000 +800008b8: 00000013 nop +800008bc: 00000013 nop +800008c0: 00000013 nop +800008c4: 00000013 nop +800008c8: 00000013 nop +800008cc: 00000013 nop +800008d0: 00000013 nop +800008d4: 00000013 nop +800008d8: 20000093 li ra,512 +800008dc: 1440b073 csrc sip,ra +800008e0: 344021f3 csrr gp,mip +800008e4: f00120b7 lui ra,0xf0012 +800008e8: 00000113 li sp,0 +800008ec: 0020a023 sw sp,0(ra) # f0012000 +800008f0: 00000013 nop +800008f4: 00000013 nop +800008f8: 00000013 nop +800008fc: 00000013 nop +80000900: 00000013 nop +80000904: 00000013 nop +80000908: 00000013 nop +8000090c: 00000013 nop +80000910: 20000093 li ra,512 +80000914: 1440b073 csrc sip,ra +80000918: 344021f3 csrr gp,mip +8000091c: f00120b7 lui ra,0xf0012 +80000920: 00000113 li sp,0 +80000924: 0020a023 sw sp,0(ra) # f0012000 +80000928: 00000013 nop +8000092c: 00000013 nop +80000930: 00000013 nop +80000934: 00000013 nop +80000938: 00000013 nop +8000093c: 00000013 nop +80000940: 00000013 nop +80000944: 00000013 nop +80000948: 20000093 li ra,512 +8000094c: 1440a073 csrs sip,ra +80000950: 344021f3 csrr gp,mip +80000954: f00120b7 lui ra,0xf0012 +80000958: 00100113 li sp,1 +8000095c: 0020a023 sw sp,0(ra) # f0012000 +80000960: 00000013 nop +80000964: 00000013 nop +80000968: 00000013 nop +8000096c: 00000013 nop +80000970: 00000013 nop +80000974: 00000013 nop +80000978: 00000013 nop +8000097c: 00000013 nop +80000980: 20000093 li ra,512 +80000984: 1440a073 csrs sip,ra +80000988: 344021f3 csrr gp,mip +8000098c: f00120b7 lui ra,0xf0012 +80000990: 00000113 li sp,0 +80000994: 0020a023 sw sp,0(ra) # f0012000 +80000998: 00000013 nop +8000099c: 00000013 nop +800009a0: 00000013 nop +800009a4: 00000013 nop +800009a8: 00000013 nop +800009ac: 00000013 nop +800009b0: 00000013 nop +800009b4: 00000013 nop + +800009b8 : +800009b8: 01800e13 li t3,24 +800009bc: 00200093 li ra,2 +800009c0: 3040a073 csrs mie,ra +800009c4: 3440a073 csrs mip,ra +800009c8: 3000a073 csrs mstatus,ra +800009cc: 00100e93 li t4,1 +800009d0: 00000f17 auipc t5,0x0 +800009d4: 03cf0f13 addi t5,t5,60 # 80000a0c +800009d8: 000020b7 lui ra,0x2 +800009dc: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +800009e0: 00001137 lui sp,0x1 +800009e4: 80010113 addi sp,sp,-2048 # 800 <_start-0x7ffff800> +800009e8: 3000b073 csrc mstatus,ra +800009ec: 30012073 csrs mstatus,sp +800009f0: 00000097 auipc ra,0x0 +800009f4: 01408093 addi ra,ra,20 # 80000a04 +800009f8: 34109073 csrw mepc,ra +800009fc: 30200073 mret +80000a00: 0280006f j 80000a28 + +80000a04 : +80000a04: 10500073 wfi +80000a08: 0200006f j 80000a28 + +80000a0c : +80000a0c: 01900e13 li t3,25 +80000a10: 00000f17 auipc t5,0x0 +80000a14: 014f0f13 addi t5,t5,20 # 80000a24 +80000a18: 30046073 csrsi mstatus,8 +80000a1c: 10500073 wfi +80000a20: 0080006f j 80000a28 + +80000a24 : +80000a24: 0100006f j 80000a34 + +80000a28 : +80000a28: f0100137 lui sp,0xf0100 +80000a2c: f2410113 addi sp,sp,-220 # f00fff24 +80000a30: 01c12023 sw t3,0(sp) + +80000a34 : +80000a34: f0100137 lui sp,0xf0100 +80000a38: f2010113 addi sp,sp,-224 # f00fff20 +80000a3c: 00012023 sw zero,0(sp) + +80000a40 : +80000a40: fe0e84e3 beqz t4,80000a28 +80000a44: 342020f3 csrr ra,mcause +80000a48: 341020f3 csrr ra,mepc +80000a4c: 300020f3 csrr ra,mstatus +80000a50: 343020f3 csrr ra,mbadaddr +80000a54: 08000093 li ra,128 +80000a58: 3000b073 csrc mstatus,ra +80000a5c: 00200093 li ra,2 +80000a60: fc1e8ae3 beq t4,ra,80000a34 +80000a64: 000020b7 lui ra,0x2 +80000a68: 80008093 addi ra,ra,-2048 # 1800 <_start-0x7fffe800> +80000a6c: 3000a073 csrs mstatus,ra +80000a70: 341f1073 csrw mepc,t5 +80000a74: 30200073 mret + +80000a78 : +80000a78: fa0e88e3 beqz t4,80000a28 +80000a7c: 142020f3 csrr ra,scause +80000a80: 141020f3 csrr ra,sepc +80000a84: 100020f3 csrr ra,sstatus +80000a88: 143020f3 csrr ra,sbadaddr +80000a8c: 00000073 ecall +80000a90: 00000013 nop +80000a94: 00000013 nop +80000a98: 00000013 nop +80000a9c: 00000013 nop +80000aa0: 00000013 nop +80000aa4: 00000013 nop diff --git a/src/test/cpp/raw/deleg/build/deleg.hex b/src/test/cpp/raw/deleg/build/deleg.hex index ba5fc06..9290e85 100644 --- a/src/test/cpp/raw/deleg/build/deleg.hex +++ b/src/test/cpp/raw/deleg/build/deleg.hex @@ -1,122 +1,174 @@ :0200000480007A -:10000000930E1000970000009380C06F73905030E3 -:10001000970000009380807273905010B71001F029 -:100020001301000023A02000130E1000170F000082 -:10003000130FCF0073000000130E2000B720000044 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:00000001FF diff --git a/src/test/cpp/raw/deleg/src/crt.S b/src/test/cpp/raw/deleg/src/crt.S index 86dd58f..f88d13f 100644 --- a/src/test/cpp/raw/deleg/src/crt.S +++ b/src/test/cpp/raw/deleg/src/crt.S @@ -10,11 +10,28 @@ li x1, 0xF0011000; \ li x2, value; \ sw x2, 0(x1); \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + #define externalInterruptS(value) \ li x1, 0xF0012000; \ li x2, value; \ sw x2, 0(x1); \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ + nop; \ diff --git a/src/test/scala/vexriscv/DhrystoneBench.scala b/src/test/scala/vexriscv/DhrystoneBench.scala index 1034aed..d23c4e1 100644 --- a/src/test/scala/vexriscv/DhrystoneBench.scala +++ b/src/test/scala/vexriscv/DhrystoneBench.scala @@ -102,9 +102,9 @@ class DhrystoneBench extends FunSuite{ getDmips( name = "GenLinuxBalenced", gen = LinuxGen.main(Array.fill[String](0)("")), - testCmd = "make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes MMU=no CSR=yes CSR_SKIP_TEST=yes DEBUG_PLUGIN=no COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=10 TRACE=no COREMARK=yes LINUX_REGRESSION=no" + testCmd = "make clean run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yes SUPERVISOR=yes MMU=no CSR=yes CSR_SKIP_TEST=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=10 TRACE=no COREMARK=yes LINUX_REGRESSION=no" ) - + //make run IBUS=CACHED DBUS=CACHED DEBUG_PLUGIN=STD DHRYSTONE=yess SUPERVISOR=yes CSR=yes COMPRESSED=no MUL=yes DIV=yes LRSC=yes AMO=yes REDO=1 TRACE=no LINUX_REGRESSION=yes SEED=42 test("final_report") {