From 9a3510f63df421d8abe0a09b842a0226d6a033f8 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Thu, 27 Sep 2018 19:03:57 +0200
Subject: [PATCH] Map all supervisor registers

---
 src/main/scala/vexriscv/Riscv.scala           | 12 ++++++++++
 .../scala/vexriscv/plugin/CsrPlugin.scala     | 22 +++++++++++++++++++
 2 files changed, 34 insertions(+)

diff --git a/src/main/scala/vexriscv/Riscv.scala b/src/main/scala/vexriscv/Riscv.scala
index 57251a4..f41e2c2 100644
--- a/src/main/scala/vexriscv/Riscv.scala
+++ b/src/main/scala/vexriscv/Riscv.scala
@@ -131,6 +131,18 @@ object Riscv{
     def MCYCLEH   = 0xB80 // MRW Upper 32 bits of mcycle, RV32I only.
     def MINSTRETH = 0xB82 // MRW Upper 32 bits of minstret, RV32I only.
 
+    val SSTATUS     = 0x100
+    val SIE         = 0x104
+    val STVEC       = 0x105
+    val SCOUNTEREN  = 0x106
+    val SSCRATCH    = 0x140
+    val SEPC        = 0x141
+    val SCAUSE      = 0x142
+    val SBADADDR    = 0x143
+    val SIP         = 0x144
+    val SATP        = 0x180
+
+
 
     def UCYCLE    = 0xC00 // UR Machine ucycle counter.
   }
diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index 81f8531..276fb53 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -51,6 +51,13 @@ case class CsrPluginConfig(
                             wfiGen              : Boolean,
                             ecallGen            : Boolean,
                             sscratchGen         : Boolean = false,
+                            stvecAccess         : CsrAccess = CsrAccess.NONE,
+                            sepcAccess          : CsrAccess = CsrAccess.NONE,
+                            scauseAccess        : CsrAccess = CsrAccess.NONE,
+                            sbadaddrAccess      : CsrAccess = CsrAccess.NONE,
+                            scycleAccess        : CsrAccess = CsrAccess.NONE,
+                            sinstretAccess      : CsrAccess = CsrAccess.NONE,
+                            satpAccess          : CsrAccess = CsrAccess.NONE,
                             deterministicInteruptionEntry : Boolean = false //Only used for simulatation purposes
 
                           ){
@@ -380,6 +387,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
       if(mhartid   != null) READ_ONLY(CSR.MHARTID  , U(mhartid  ))
 
       //Machine CSR
+      //TODO machine mode shadow supervisor
       misaAccess(CSR.MISA, xlen-2 -> misa.base , 0 -> misa.extensions)
       READ_ONLY(CSR.MIP, 11 -> mip.MEIP, 7 -> mip.MTIP)
       READ_WRITE(CSR.MIP, 3 -> mip.MSIP)
@@ -396,6 +404,20 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
       minstretAccess(CSR.MINSTRET, minstret(31 downto 0))
       minstretAccess(CSR.MINSTRETH, minstret(63 downto 32))
 
+      //Supervisor CSR
+      READ_ONLY(CSR.SIP, 9 -> sip.SEIP, 5 -> sip.STIP)
+      READ_WRITE(CSR.SIP, 1 -> sip.SSIP)
+      READ_WRITE(CSR.SIE, 9 -> sie.SEIE, 5 -> sie.STIE, 1 -> sie.SSIE)
+
+      stvecAccess(CSR.STVEC, stvec)
+      sepcAccess(CSR.SEPC, sepc)
+      READ_WRITE(CSR.SSTATUS,9 -> sstatus.SPP, 5 -> sstatus.SPIE, 1 -> sstatus.SIE)
+      if(sscratchGen) READ_WRITE(CSR.SSCRATCH, sscratch)
+      scauseAccess(CSR.SCAUSE, xlen-1 -> scause.interrupt, 0 -> scause.exceptionCode)
+      sbadaddrAccess(CSR.SBADADDR, stval)
+      satpAccess(CSR.SATP, 31 -> satp.MODE, 22 -> satp.ASID, 0 -> satp.PPN)
+
+
       //User CSR
       ucycleAccess(CSR.UCYCLE, mcycle(31 downto 0))