From 9a4c35d7b62aa6a8049bc7fc9a1417267d996dbf Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sat, 8 Apr 2017 18:34:44 +0200 Subject: [PATCH] IBusCachedPlugin twoStage config fix --- src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala b/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala index 87fc59b..97d623a 100644 --- a/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala +++ b/src/main/scala/SpinalRiscv/Plugin/IBusCachedPlugin.scala @@ -370,6 +370,7 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ val valid = RegNext(lineLoader.waysWritePort.valid) val address = RegNext(lineLoader.request.addr(tagLineRange) @@ lineLoader.wordIndex @@ U"00") val data = RegNext(lineLoader.waysWritePort.data) + val wasLoaded = RegNext(lineLoader.loadedWords) } @@ -385,8 +386,8 @@ class InstructionCache(p : InstructionCacheConfig) extends Component{ fetchInstructionValid := True fetchInstructionValue := loadedWord.data } otherwise{ - fetchInstructionValid := waysHitValid - fetchInstructionValue := waysHitWord + fetchInstructionValid := waysHitValid || (loadedWord.address(tagLineRange) === io.cpu.fetch.address(tagLineRange) && loadedWord.wasLoaded(io.cpu.fetch.address(wordRange))) + fetchInstructionValue := waysHitWord //Not multi way (wasloaded) }