diff --git a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala
index a34dc46..0b7bcd2 100644
--- a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala
@@ -105,14 +105,9 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,
       if(x0Init) {
         val boot = RegNext(False) init (True)
         regFileWrite.valid setWhen (boot)
-        if (writeStage != execute) {
-          inputInit[Bits](REGFILE_WRITE_DATA, 0)
-          inputInit[Bits](INSTRUCTION, 0)
-        } else {
-          when(boot) {
-            regFileWrite.address := 0
-            regFileWrite.data := 0
-          }
+        when(boot) {
+          regFileWrite.address := 0
+          regFileWrite.data := 0
         }
       }
     }