From 9ac1d3d59eec26ff6a2904b3dc845d00d3926412 Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Sat, 13 Apr 2019 10:40:53 +0200
Subject: [PATCH] riscv software model without RVC now trap on RVC instruction
 before pcWrite + 2

---
 src/test/cpp/regression/main.cpp | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
index 4cddfe7..d42f56c 100644
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@@ -957,6 +957,9 @@ public:
 			default: ilegalInstruction(); break;
 			}
 		} else {
+			#ifndef COMPRESSED
+	        ilegalInstruction(); return;
+			#endif
 			switch((iBits(0, 2) << 3) + iBits(13, 3)){
 			case 0: rfWrite(i16_addr2, rf_sp + i16_addi4spn_imm); pcWrite(pc + 2); break;
 			case 2:  {