From 9acc5ddc1c444aa2da9100b1edc99eb5c1dc6b98 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 6 Feb 2023 11:44:44 +0100 Subject: [PATCH] Fix FPU access trap on fs = 0 #297 --- src/main/scala/vexriscv/plugin/FpuPlugin.scala | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/FpuPlugin.scala b/src/main/scala/vexriscv/plugin/FpuPlugin.scala index b3373e3..894d426 100644 --- a/src/main/scala/vexriscv/plugin/FpuPlugin.scala +++ b/src/main/scala/vexriscv/plugin/FpuPlugin.scala @@ -233,10 +233,15 @@ class FpuPlugin(externalFpu : Boolean = false, decode plug new Area{ import decode._ + val trap = decode.input(FPU_ENABLE) && csr.fs === 0 && !stagesFromExecute.map(_.arbitration.isValid).orR + when(trap){ + pipeline.service(classOf[DecoderService]).forceIllegal() + } + //Maybe it might be better to not fork before fire to avoid RF stall on commits val forked = Reg(Bool) setWhen(port.cmd.fire) clearWhen(!arbitration.isStuck) init(False) - val hazard = csr.pendings.msb || csr.csrActive + val hazard = csr.pendings.msb || csr.csrActive || csr.fs === 0 arbitration.haltItself setWhen(arbitration.isValid && input(FPU_ENABLE) && hazard) arbitration.haltItself setWhen(port.cmd.isStall)