diff --git a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
index 723ea7d..3ff3334 100644
--- a/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
+++ b/src/main/scala/vexriscv/VexRiscvBmbGenerator.scala
@@ -113,7 +113,7 @@ case class VexRiscvBmbGenerator()(implicit interconnectSmp: BmbInterconnectGener
 
         withDebug.get match {
           case DEBUG_JTAG => jtag <> plugin.io.bus.fromJtag()
-          case DEBUG_JTAG_CTRL => jtagInstructionCtrl <> plugin.io.bus.fromJtagInstructionCtrl(jtagClockDomain)
+          case DEBUG_JTAG_CTRL => jtagInstructionCtrl <> plugin.io.bus.fromJtagInstructionCtrl(jtagClockDomain, 0)
           case DEBUG_BUS => debugBus <> plugin.io.bus
           case DEBUG_BMB => debugBmb >> plugin.io.bus.fromBmb()
         }
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
index 54941d4..743d2c2 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -26,6 +26,7 @@ import spinal.lib.generator._
 import vexriscv.ip.fpu.FpuParameter
 
 case class VexRiscvSmpClusterParameter(cpuConfigs : Seq[VexRiscvConfig],
+                                       jtagHeaderIgnoreWidth : Int,
                                        withExclusiveAndInvalidation : Boolean,
                                        forcePeripheralWidth : Boolean = true,
                                        outOfOrderDecoder : Boolean = true,
@@ -51,7 +52,7 @@ class VexRiscvSmpClusterBase(p : VexRiscvSmpClusterParameter) extends Area with
 
   implicit val interconnect = BmbInterconnectGenerator()
 
-  val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator()
+  val debugBridge = debugCd.outputClockDomain on JtagInstructionDebuggerGenerator(p.jtagHeaderIgnoreWidth)
   debugBridge.jtagClockDomain.load(ClockDomain.external("jtag", withReset = false))
 
   val debugPort = Handle(debugBridge.logic.jtagBridge.io.ctrl.toIo)
diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
index 7a20b30..4cd4917 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpLitexCluster.scala
@@ -175,7 +175,8 @@ object VexRiscvLitexSmpClusterCmdGen extends App {
       withExclusiveAndInvalidation = coherency,
       forcePeripheralWidth = !wishboneMemory,
       outOfOrderDecoder = outOfOrderDecoder,
-      fpu = fpu
+      fpu = fpu,
+      jtagHeaderIgnoreWidth = 0
     ),
     liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = liteDramWidth),
     liteDramMapping = SizeMapping(0x40000000l, 0x40000000l),
@@ -250,7 +251,8 @@ object VexRiscvLitexSmpClusterOpenSbi extends App{
           resetVector = 0x80000000l
         )
       },
-      withExclusiveAndInvalidation = true
+      withExclusiveAndInvalidation = true,
+      jtagHeaderIgnoreWidth = 0
     ),
     liteDram = LiteDramNativeParameter(addressWidth = 32, dataWidth = 128),
     liteDramMapping = SizeMapping(0x80000000l, 0x70000000l),
diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
index d96d312..094de17 100644
--- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
@@ -567,8 +567,8 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
         }
       }
 
-      if(!earlyInjection && !emitCmdInMemoryStage && config.withWriteBackStage)
-        assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(MEMORY_STORE) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend")
+//      if(!earlyInjection && !emitCmdInMemoryStage && config.withWriteBackStage)
+//        assert(!(arbitration.isValid && input(MEMORY_ENABLE) && !input(MEMORY_STORE) && arbitration.isStuck),"DBusSimplePlugin doesn't allow writeback stage stall when read happend")
 
       //formal
       insert(FORMAL_MEM_RDATA) := input(MEMORY_READ_DATA)
diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
index cc7ca33..87d4f56 100644
--- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
@@ -137,13 +137,13 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
     jtagBridge.io.jtag
   }
 
-  def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain): JtagTapInstructionCtrl ={
+  def fromJtagInstructionCtrl(jtagClockDomain : ClockDomain, jtagHeaderIgnoreWidth : Int): JtagTapInstructionCtrl ={
     val jtagConfig = SystemDebuggerConfig(
       memAddressWidth = 32,
       memDataWidth    = 32,
       remoteCmdWidth  = 1
     )
-    val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain)
+    val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain, jtagHeaderIgnoreWidth)
     val debugger = new SystemDebugger(jtagConfig)
     debugger.io.remote <> jtagBridge.io.remote
     debugger.io.mem <> this.from(jtagConfig)
@@ -151,13 +151,13 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{
     jtagBridge.io.ctrl
   }
 
-  def fromBscane2(usedId : Int): Unit ={
+  def fromBscane2(usedId : Int, jtagHeaderIgnoreWidth : Int): Unit ={
     val jtagConfig = SystemDebuggerConfig()
 
     val bscane2 = BSCANE2(usedId)
     val jtagClockDomain = ClockDomain(bscane2.TCK)
 
-    val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain)
+    val jtagBridge = new JtagBridgeNoTap(jtagConfig, jtagClockDomain, jtagHeaderIgnoreWidth)
     jtagBridge.io.ctrl << bscane2.toJtagTapInstructionCtrl()
 
     val debugger = new SystemDebugger(jtagConfig)