From 9c7e089329f41d25d24255f3897ec18ef315be65 Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Fri, 17 Aug 2018 20:38:33 +0200
Subject: [PATCH] Fix ExternalInterruptArrayPlugin CSR ids

---
 .../vexriscv/plugin/ExternalInterruptArrayPlugin.scala      | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala b/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala
index b205f0f..ee200ea 100644
--- a/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/ExternalInterruptArrayPlugin.scala
@@ -3,7 +3,7 @@ package vexriscv.plugin
 import spinal.core._
 import vexriscv.VexRiscv
 
-class ExternalInterruptArrayPlugin(arrayWidth : Int = 32) extends Plugin[VexRiscv]{
+class ExternalInterruptArrayPlugin(arrayWidth : Int = 32, maskCsrId : Int = 0xBC0, pendingsCsrId : Int = 0xFC0) extends Plugin[VexRiscv]{
   var externalInterruptArray : Bits = null
 
   override def setup(pipeline: VexRiscv): Unit = {
@@ -15,7 +15,7 @@ class ExternalInterruptArrayPlugin(arrayWidth : Int = 32) extends Plugin[VexRisc
     val mask = Reg(Bits(arrayWidth bits)) init(0)
     val pendings = mask & RegNext(externalInterruptArray)
     csr.externalInterrupt.asDirectionLess() := pendings.orR
-    csr.rw(0x330, mask)
-    csr.r(0x360, pendings)
+    csr.rw(maskCsrId, mask)
+    csr.r(pendingsCsrId, pendings)
   }
 }