diff --git a/src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala b/src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala
new file mode 100644
index 0000000..e6496b1
--- /dev/null
+++ b/src/main/scala/vexriscv/demo/GenFullWithRiscvPrivilegedDebugJtag.scala
@@ -0,0 +1,101 @@
+package vexriscv.demo
+
+import spinal.core._
+import spinal.lib.cpu.riscv.debug.DebugTransportModuleParameter
+import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig}
+import vexriscv.plugin._
+import vexriscv.{VexRiscv, VexRiscvConfig, plugin}
+
+/**
+ * Created by spinalvm on 15.06.17.
+ */
+object GenFullWithRiscvPrivilegedDebugJtag extends App{
+  def config = VexRiscvConfig(
+    plugins = List(
+      new IBusCachedPlugin(
+        prediction = DYNAMIC,
+        config = InstructionCacheConfig(
+          cacheSize = 4096,
+          bytePerLine =32,
+          wayCount = 1,
+          addressWidth = 32,
+          cpuDataWidth = 32,
+          memDataWidth = 32,
+          catchIllegalAccess = true,
+          catchAccessFault = true,
+          asyncTagMemory = false,
+          twoCycleRam = true,
+          twoCycleCache = true
+        ),
+        memoryTranslatorPortConfig = MmuPortConfig(
+          portTlbSize = 4
+        )
+      ),
+      new DBusCachedPlugin(
+        config = new DataCacheConfig(
+          cacheSize         = 4096,
+          bytePerLine       = 32,
+          wayCount          = 1,
+          addressWidth      = 32,
+          cpuDataWidth      = 32,
+          memDataWidth      = 32,
+          catchAccessError  = true,
+          catchIllegal      = true,
+          catchUnaligned    = true
+        ),
+        memoryTranslatorPortConfig = MmuPortConfig(
+          portTlbSize = 6
+        )
+      ),
+      new MmuPlugin(
+        virtualRange = _(31 downto 28) === 0xC,
+        ioRange      = _(31 downto 28) === 0xF
+      ),
+      new DecoderSimplePlugin(
+        catchIllegalInstruction = true
+      ),
+      new RegFilePlugin(
+        regFileReadyKind = plugin.SYNC,
+        zeroBoot = false
+      ),
+      new IntAluPlugin,
+      new SrcPlugin(
+        separatedAddSub = false,
+        executeInsertion = true
+      ),
+      new FullBarrelShifterPlugin,
+      new HazardSimplePlugin(
+        bypassExecute           = true,
+        bypassMemory            = true,
+        bypassWriteBack         = true,
+        bypassWriteBackBuffer   = true,
+        pessimisticUseSrc       = false,
+        pessimisticWriteRegFile = false,
+        pessimisticAddressMatch = false
+      ),
+      new MulPlugin,
+      new DivPlugin,
+      new CsrPlugin(CsrPluginConfig.small(0x80000020l).copy(withPrivilegedDebug = true)), //withPrivilegedDebug is required
+      new EmbeddedRiscvJtag(
+        DebugTransportModuleParameter(
+          addressWidth = 7,
+          version      = 1,
+          idle         = 7
+        ),
+        withTap = true,
+        withTunneling = false
+      ),
+      new BranchPlugin(
+        earlyBranch = false,
+        catchAddressMisaligned = true
+      ),
+      new YamlPlugin("cpu0.yaml")
+    )
+  )
+
+  def cpu() = new VexRiscv(
+    config
+  )
+
+  SpinalVerilog(cpu())
+}
diff --git a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
index f793755..c75c4d1 100644
--- a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
+++ b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
@@ -30,7 +30,7 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
   override def setup(pipeline: VexRiscv): Unit = {
     jtag = withTap generate slave(Jtag()).setName("jtag")
     jtagInstruction = !withTap generate slave(JtagTapInstructionCtrl()).setName("jtagInstruction")
-    ndmreset = Bool().setName("ndmreset")
+    ndmreset = out(Bool()).setName("ndmreset")
   }
 
   override def build(pipeline: VexRiscv): Unit = {