From 9fe4e1d54da02bad23073736ca77d8d6e2e90a0a Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Sun, 23 Jul 2017 13:28:17 +0200 Subject: [PATCH] Package refractoring VexRiscv -> vexriscv Plugin -> plugin --- README.md | 27 +++++++++-------- .../{VexRiscv => vexriscv}/Pipeline.scala | 4 +-- .../scala/{VexRiscv => vexriscv}/Riscv.scala | 2 +- .../{VexRiscv => vexriscv}/Services.scala | 2 +- .../scala/{VexRiscv => vexriscv}/Stage.scala | 2 +- .../TestsWorkspace.scala | 14 ++++----- .../{VexRiscv => vexriscv}/VexRiscv.scala | 4 +-- .../{VexRiscv => vexriscv}/demo/Briey.scala | 28 ++++------------- .../demo/CustomInstruction.scala | 6 ++-- .../{VexRiscv => vexriscv}/demo/GenFull.scala | 10 +++---- .../demo/GenFullNoMmu.scala | 10 +++---- .../demo/GenFullNoMmuNoCache.scala | 10 +++---- .../demo/GenSmallAndPerformant.scala | 8 ++--- .../demo/GenSmallest.scala | 8 ++--- .../demo/GenSmallestNoCsr.scala | 8 ++--- .../demo/SynthesisBench.scala | 2 +- .../demo/VexRiscvAvalon.scala | 10 +++---- .../{VexRiscv => vexriscv}/ip/DataCache.scala | 4 +-- .../ip/InstructionCache.scala | 4 +-- .../plugin}/BranchPlugin.scala | 6 ++-- .../plugin}/CsrPlugin.scala | 6 ++-- .../plugin}/DBusCachedPlugin.scala | 6 ++-- .../plugin}/DBusSimplePlugin.scala | 4 +-- .../plugin}/DebugPlugin.scala | 30 ++++++++++++++++--- .../plugin}/DecoderSimplePlugin.scala | 4 +-- .../plugin}/DivPlugin.scala | 4 +-- .../plugin}/HazardPessimisticPlugin.scala | 4 +-- .../plugin}/HazardSimplePlugin.scala | 4 +-- .../plugin}/IBusCachedPlugin.scala | 6 ++-- .../plugin}/IBusSimplePlugin.scala | 4 +-- .../plugin}/IntAluPlugin.scala | 4 +-- .../plugin}/MemoryTranslatorPlugin.scala | 4 +-- .../plugin}/MulPlugin.scala | 6 ++-- .../plugin}/PcManagerSimplePlugin.scala | 4 +-- .../Plugin => vexriscv/plugin}/Plugin.scala | 4 +-- .../plugin}/RegFilePlugin.scala | 4 +-- .../plugin}/ShiftPlugins.scala | 4 +-- .../SingleInstructionLimiterPlugin.scala | 4 +-- .../plugin}/SrcPlugin.scala | 4 +-- .../StaticMemoryTranslatorPlugin.scala | 4 +-- .../plugin}/YamlPlugin.scala | 4 +-- 41 files changed, 148 insertions(+), 139 deletions(-) rename src/main/scala/{VexRiscv => vexriscv}/Pipeline.scala (99%) rename src/main/scala/{VexRiscv => vexriscv}/Riscv.scala (99%) rename src/main/scala/{VexRiscv => vexriscv}/Services.scala (99%) rename src/main/scala/{VexRiscv => vexriscv}/Stage.scala (99%) rename src/main/scala/{VexRiscv => vexriscv}/TestsWorkspace.scala (97%) rename src/main/scala/{VexRiscv => vexriscv}/VexRiscv.scala (98%) rename src/main/scala/{VexRiscv => vexriscv}/demo/Briey.scala (92%) rename src/main/scala/{VexRiscv => vexriscv}/demo/CustomInstruction.scala (96%) rename src/main/scala/{VexRiscv => vexriscv}/demo/GenFull.scala (93%) rename src/main/scala/{VexRiscv => vexriscv}/demo/GenFullNoMmu.scala (92%) rename src/main/scala/{VexRiscv => vexriscv}/demo/GenFullNoMmuNoCache.scala (88%) rename src/main/scala/{VexRiscv => vexriscv}/demo/GenSmallAndPerformant.scala (91%) rename src/main/scala/{VexRiscv => vexriscv}/demo/GenSmallest.scala (91%) rename src/main/scala/{VexRiscv => vexriscv}/demo/GenSmallestNoCsr.scala (90%) rename src/main/scala/{VexRiscv => vexriscv}/demo/SynthesisBench.scala (99%) rename src/main/scala/{VexRiscv => vexriscv}/demo/VexRiscvAvalon.scala (96%) rename src/main/scala/{VexRiscv => vexriscv}/ip/DataCache.scala (99%) rename src/main/scala/{VexRiscv => vexriscv}/ip/InstructionCache.scala (99%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/BranchPlugin.scala (99%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/CsrPlugin.scala (99%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/DBusCachedPlugin.scala (99%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/DBusSimplePlugin.scala (99%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/DebugPlugin.scala (84%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/DecoderSimplePlugin.scala (99%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/DivPlugin.scala (97%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/HazardPessimisticPlugin.scala (92%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/HazardSimplePlugin.scala (98%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/IBusCachedPlugin.scala (98%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/IBusSimplePlugin.scala (98%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/IntAluPlugin.scala (99%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/MemoryTranslatorPlugin.scala (99%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/MulPlugin.scala (97%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/PcManagerSimplePlugin.scala (98%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/Plugin.scala (90%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/RegFilePlugin.scala (98%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/ShiftPlugins.scala (99%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/SingleInstructionLimiterPlugin.scala (88%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/SrcPlugin.scala (97%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/StaticMemoryTranslatorPlugin.scala (95%) rename src/main/scala/{VexRiscv/Plugin => vexriscv/plugin}/YamlPlugin.scala (91%) diff --git a/README.md b/README.md index d8feba4..3d7721b 100644 --- a/README.md +++ b/README.md @@ -24,7 +24,7 @@ This repository host an RISC-V implementation written in SpinalHDL. There is som - Optional MUL/DIV extension - Optional instruction and data caches - Optional MMU -- Optional debug extension allowing GDB debugging via an openOCD JTAG connection +- Optional debug extension allowing eclipse debugging via an GDB >> openOCD >> JTAG connection - Optional interrupts and exception handling with the Machine and the User mode from the riscv-privileged-v1.9.1 spec. - Two implementation of shift instructions, Single cycle / shiftNumber cycles - Each stage could have bypass or interlock hazard logic @@ -40,7 +40,7 @@ The hardware description of this CPU is done by using an very software oriented ## Area usage and maximal frequency The following number where obtains by synthesis the CPU as toplevel without any specific synthesis option to save area or to get better maximal frequency (neutral). -The used CPU corresponding configuration can be find in src/scala/VexRiscv/demo. +The used CPU corresponding configuration can be find in src/scala/vexriscv/demo. ``` VexRiscv smallest (RV32I, 0.47 DMIPS/Mhz, no datapath bypass, no interrupt) -> @@ -110,8 +110,8 @@ sudo make install ## CPU generation You can find two example of CPU instantiation in : -- src/main/scala/VexRiscv/GenFull.scala -- src/main/scala/VexRiscv/GenSmallest.scala +- src/main/scala/vexriscv/GenFull.scala +- src/main/scala/vexriscv/GenSmallest.scala To generate the corresponding RTL as a VexRiscv.v file, run (it could take time the first time you run it): @@ -119,10 +119,10 @@ NOTE : The VexRiscv could need the unreleased master-head of SpinalHDL. If it fail to compile, just get the SpinalHDL repository and do a "sbt publish-local" in it. ```sh -sbt "run-main VexRiscv.demo.GenFull" +sbt "run-main vexriscv.demo.GenFull" # or -sbt "run-main VexRiscv.demo.GenSmallest" +sbt "run-main vexriscv.demo.GenSmallest" ``` ## Regression tests @@ -144,7 +144,7 @@ Then you can use the https://github.com/SpinalHDL/openocd_riscv tool to create a ```sh #in the VexRiscv repository, to run the simulation on which one OpenOCD can connect itself => -sbt "run-main VexRiscv.demo.GenFull" +sbt "run-main vexriscv.demo.GenFull" cd src/test/cpp/regression make run DEBUG_PLUGIN_EXTERNAL=yes @@ -165,7 +165,7 @@ continue You can use the eclipse + zilin embedded CDT plugin to do it (http://opensource.zylin.com/embeddedcdt.html). Tested with Helios Service Release 2 and the corresponding zylin plugin. ## Briey SoC -As a demonstrator, a SoC named Briey is implemented in src/main/scala/VexRiscv/demo/Briey.scala. This SoC is very similar to the Pinsec one : +As a demonstrator, a SoC named Briey is implemented in src/main/scala/vexriscv/demo/Briey.scala. This SoC is very similar to the Pinsec one : @@ -173,7 +173,7 @@ As a demonstrator, a SoC named Briey is implemented in src/main/scala/VexRiscv/d To generate the Briey SoC Hardware : ```sh -sbt "run-main VexRiscv.demo.Briey" +sbt "run-main vexriscv.demo.Briey" ``` To run the verilator simulation of the Briey SoC which can be then connected to OpenOCD/GDB, first get those dependencies : @@ -240,9 +240,12 @@ echo -e "\\nRISC-V Toolchain installation completed!" ## CPU parametrization and instantiation example -You can find many example of different config in the https://github.com/SpinalHDL/VexRiscv/tree/master/src/main/scala/VexRiscv/demo folder. There is one : +You can find many example of different config in the https://github.com/SpinalHDL/VexRiscv/tree/master/src/main/scala/vexriscv/demo folder. There is one : ```scala +import vexriscv._ +import vexriscv.plugin._ + //Instanciate one VexRiscv val cpu = new VexRiscv( //Provide a configuration instance @@ -297,8 +300,8 @@ There is an example of an simple plugin which add an simple SIMD_ADD instruction ```scala import spinal.core._ -import VexRiscv.Plugin.Plugin -import VexRiscv.{Stageable, DecoderService, VexRiscv} +import vexriscv.plugin.Plugin +import vexriscv.{Stageable, DecoderService, VexRiscv} //This plugin example will add a new instruction named SIMD_ADD which do the following : // diff --git a/src/main/scala/VexRiscv/Pipeline.scala b/src/main/scala/vexriscv/Pipeline.scala similarity index 99% rename from src/main/scala/VexRiscv/Pipeline.scala rename to src/main/scala/vexriscv/Pipeline.scala index 1879e50..88efe2a 100644 --- a/src/main/scala/VexRiscv/Pipeline.scala +++ b/src/main/scala/vexriscv/Pipeline.scala @@ -1,6 +1,6 @@ -package VexRiscv +package vexriscv -import VexRiscv.Plugin._ +import vexriscv.plugin._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Riscv.scala b/src/main/scala/vexriscv/Riscv.scala similarity index 99% rename from src/main/scala/VexRiscv/Riscv.scala rename to src/main/scala/vexriscv/Riscv.scala index 1b1af88..9c83033 100644 --- a/src/main/scala/VexRiscv/Riscv.scala +++ b/src/main/scala/vexriscv/Riscv.scala @@ -1,4 +1,4 @@ -package VexRiscv +package vexriscv import spinal.core._ diff --git a/src/main/scala/VexRiscv/Services.scala b/src/main/scala/vexriscv/Services.scala similarity index 99% rename from src/main/scala/VexRiscv/Services.scala rename to src/main/scala/vexriscv/Services.scala index 72890b3..d0c8280 100644 --- a/src/main/scala/VexRiscv/Services.scala +++ b/src/main/scala/vexriscv/Services.scala @@ -1,4 +1,4 @@ -package VexRiscv +package vexriscv import java.util diff --git a/src/main/scala/VexRiscv/Stage.scala b/src/main/scala/vexriscv/Stage.scala similarity index 99% rename from src/main/scala/VexRiscv/Stage.scala rename to src/main/scala/vexriscv/Stage.scala index b3c4670..39ccf87 100644 --- a/src/main/scala/VexRiscv/Stage.scala +++ b/src/main/scala/vexriscv/Stage.scala @@ -1,4 +1,4 @@ -package VexRiscv +package vexriscv import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala similarity index 97% rename from src/main/scala/VexRiscv/TestsWorkspace.scala rename to src/main/scala/vexriscv/TestsWorkspace.scala index c4f8dd2..3dfa4fc 100644 --- a/src/main/scala/VexRiscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -16,13 +16,13 @@ * License along with this library. */ -package VexRiscv +package vexriscv -import VexRiscv.Plugin._ -import VexRiscv.demo.SimdAddPlugin +import vexriscv.plugin._ +import vexriscv.demo.SimdAddPlugin import spinal.core._ import spinal.lib._ -import VexRiscv.ip._ +import vexriscv.ip._ import spinal.lib.bus.avalon.AvalonMM import spinal.lib.eda.altera.{InterruptReceiverTag, ResetEmitterTag} @@ -90,7 +90,7 @@ object TestsWorkspace { catchIllegalInstruction = true ), new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = true ), new IntAluPlugin, @@ -140,7 +140,7 @@ object TestsWorkspace { catchIllegalInstruction = false ), new RegFilePlugin( - regFileReadyKind = Plugin.ASYNC, + regFileReadyKind = plugin.ASYNC, zeroBoot = false ), new IntAluPlugin, @@ -191,7 +191,7 @@ object TestsWorkspace { catchIllegalInstruction = true ), new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = true ), new IntAluPlugin, diff --git a/src/main/scala/VexRiscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala similarity index 98% rename from src/main/scala/VexRiscv/VexRiscv.scala rename to src/main/scala/vexriscv/VexRiscv.scala index dc07241..bc83a46 100644 --- a/src/main/scala/VexRiscv/VexRiscv.scala +++ b/src/main/scala/vexriscv/VexRiscv.scala @@ -1,6 +1,6 @@ -package VexRiscv +package vexriscv -import VexRiscv.Plugin._ +import vexriscv.plugin._ import spinal.core._ case class VexRiscvConfig(plugins : Seq[Plugin[VexRiscv]]){ diff --git a/src/main/scala/VexRiscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala similarity index 92% rename from src/main/scala/VexRiscv/demo/Briey.scala rename to src/main/scala/vexriscv/demo/Briey.scala index d5f4338..343044d 100644 --- a/src/main/scala/VexRiscv/demo/Briey.scala +++ b/src/main/scala/vexriscv/demo/Briey.scala @@ -1,9 +1,9 @@ -package VexRiscv.demo +package vexriscv.demo -import VexRiscv.Plugin._ -import VexRiscv._ -import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig} +import vexriscv.plugin._ +import vexriscv._ +import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba3.apb._ @@ -231,7 +231,7 @@ class Briey(config: BrieyConfig) extends Component{ catchIllegalInstruction = true ), new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = false ), new IntAluPlugin, @@ -367,28 +367,12 @@ class Briey(config: BrieyConfig) extends Component{ ) ) - //Add JTAG - val jtagConfig = SystemDebuggerConfig( - memAddressWidth = 32, - memDataWidth = 32, - remoteCmdWidth = 1 - ) - val jtagBridge = new JtagBridge(jtagConfig) - val debugger = new SystemDebugger(jtagConfig) - debugger.io.remote <> jtagBridge.io.remote - debugger.io.mem.cmd.valid <> core.debugBus.cmd.valid - debugger.io.mem.cmd.ready <> core.debugBus.cmd.ready - debugger.io.mem.cmd.wr <> core.debugBus.cmd.wr - debugger.io.mem.cmd.address.resized <> core.debugBus.cmd.address - debugger.io.mem.cmd.data <> core.debugBus.cmd.data - debugger.io.mem.rsp.valid <> RegNext(core.debugBus.cmd.fire).init(False) - debugger.io.mem.rsp.payload <> core.debugBus.rsp.data + io.jtag <> core.debugBus.fromJtag() } io.gpioA <> axi.gpioACtrl.io.gpio io.gpioB <> axi.gpioBCtrl.io.gpio io.timerExternal <> axi.timerCtrl.io.external - io.jtag <> axi.jtagBridge.io.jtag io.uart <> axi.uartCtrl.io.uart io.sdram <> axi.sdramCtrl.io.sdram io.vga <> axi.vgaCtrl.io.vga diff --git a/src/main/scala/VexRiscv/demo/CustomInstruction.scala b/src/main/scala/vexriscv/demo/CustomInstruction.scala similarity index 96% rename from src/main/scala/VexRiscv/demo/CustomInstruction.scala rename to src/main/scala/vexriscv/demo/CustomInstruction.scala index a2a6208..c1bc448 100644 --- a/src/main/scala/VexRiscv/demo/CustomInstruction.scala +++ b/src/main/scala/vexriscv/demo/CustomInstruction.scala @@ -1,8 +1,8 @@ -package VexRiscv.demo +package vexriscv.demo import spinal.core._ -import VexRiscv.Plugin.Plugin -import VexRiscv.{Stageable, DecoderService, VexRiscv} +import vexriscv.plugin.Plugin +import vexriscv.{Stageable, DecoderService, VexRiscv} //This plugin example will add a new instruction named SIMD_ADD which do the following : // diff --git a/src/main/scala/VexRiscv/demo/GenFull.scala b/src/main/scala/vexriscv/demo/GenFull.scala similarity index 93% rename from src/main/scala/VexRiscv/demo/GenFull.scala rename to src/main/scala/vexriscv/demo/GenFull.scala index 3714ea8..16c8259 100644 --- a/src/main/scala/VexRiscv/demo/GenFull.scala +++ b/src/main/scala/vexriscv/demo/GenFull.scala @@ -1,8 +1,8 @@ -package VexRiscv.demo +package vexriscv.demo -import VexRiscv.Plugin._ -import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig} -import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig} +import vexriscv.plugin._ +import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} +import vexriscv.{plugin, VexRiscv, VexRiscvConfig} import spinal.core._ /** @@ -62,7 +62,7 @@ object GenFull extends App{ catchIllegalInstruction = true ), new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = true ), new IntAluPlugin, diff --git a/src/main/scala/VexRiscv/demo/GenFullNoMmu.scala b/src/main/scala/vexriscv/demo/GenFullNoMmu.scala similarity index 92% rename from src/main/scala/VexRiscv/demo/GenFullNoMmu.scala rename to src/main/scala/vexriscv/demo/GenFullNoMmu.scala index 29c8eaf..c9980a4 100644 --- a/src/main/scala/VexRiscv/demo/GenFullNoMmu.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmu.scala @@ -1,8 +1,8 @@ -package VexRiscv.demo +package vexriscv.demo -import VexRiscv.Plugin._ -import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig} -import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig} +import vexriscv.plugin._ +import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} +import vexriscv.{plugin, VexRiscv, VexRiscvConfig} import spinal.core._ /** @@ -53,7 +53,7 @@ object GenFullNoMmu extends App{ catchIllegalInstruction = true ), new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = true ), new IntAluPlugin, diff --git a/src/main/scala/VexRiscv/demo/GenFullNoMmuNoCache.scala b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala similarity index 88% rename from src/main/scala/VexRiscv/demo/GenFullNoMmuNoCache.scala rename to src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala index 0077f3d..46c8ae6 100644 --- a/src/main/scala/VexRiscv/demo/GenFullNoMmuNoCache.scala +++ b/src/main/scala/vexriscv/demo/GenFullNoMmuNoCache.scala @@ -1,8 +1,8 @@ -package VexRiscv.demo +package vexriscv.demo -import VexRiscv.Plugin._ -import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig} -import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig} +import vexriscv.plugin._ +import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} +import vexriscv.{plugin, VexRiscv, VexRiscvConfig} import spinal.core._ /** @@ -28,7 +28,7 @@ object GenFullNoMmuNoCache extends App{ catchIllegalInstruction = true ), new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = true ), new IntAluPlugin, diff --git a/src/main/scala/VexRiscv/demo/GenSmallAndPerformant.scala b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala similarity index 91% rename from src/main/scala/VexRiscv/demo/GenSmallAndPerformant.scala rename to src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala index 114c41a..2b0c8e2 100644 --- a/src/main/scala/VexRiscv/demo/GenSmallAndPerformant.scala +++ b/src/main/scala/vexriscv/demo/GenSmallAndPerformant.scala @@ -1,7 +1,7 @@ -package VexRiscv.demo +package vexriscv.demo -import VexRiscv.Plugin._ -import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig} +import vexriscv.plugin._ +import vexriscv.{plugin, VexRiscv, VexRiscvConfig} import spinal.core._ /** @@ -28,7 +28,7 @@ object GenSmallAndProductive extends App{ catchIllegalInstruction = false ), new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = true ), new IntAluPlugin, diff --git a/src/main/scala/VexRiscv/demo/GenSmallest.scala b/src/main/scala/vexriscv/demo/GenSmallest.scala similarity index 91% rename from src/main/scala/VexRiscv/demo/GenSmallest.scala rename to src/main/scala/vexriscv/demo/GenSmallest.scala index e59da09..f5dfc2b 100644 --- a/src/main/scala/VexRiscv/demo/GenSmallest.scala +++ b/src/main/scala/vexriscv/demo/GenSmallest.scala @@ -1,7 +1,7 @@ -package VexRiscv.demo +package vexriscv.demo -import VexRiscv.Plugin._ -import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig} +import vexriscv.plugin._ +import vexriscv.{plugin, VexRiscv, VexRiscvConfig} import spinal.core._ /** @@ -28,7 +28,7 @@ object GenSmallest extends App{ catchIllegalInstruction = false ), new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = true ), new IntAluPlugin, diff --git a/src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala similarity index 90% rename from src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala rename to src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala index 2f6ceca..c7df0f5 100644 --- a/src/main/scala/VexRiscv/demo/GenSmallestNoCsr.scala +++ b/src/main/scala/vexriscv/demo/GenSmallestNoCsr.scala @@ -1,7 +1,7 @@ -package VexRiscv.demo +package vexriscv.demo -import VexRiscv.Plugin._ -import VexRiscv.{Plugin, VexRiscv, VexRiscvConfig} +import vexriscv.plugin._ +import vexriscv.{plugin, VexRiscv, VexRiscvConfig} import spinal.core._ /** @@ -27,7 +27,7 @@ object GenSmallestNoCsr extends App{ catchIllegalInstruction = false ), new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = true ), new IntAluPlugin, diff --git a/src/main/scala/VexRiscv/demo/SynthesisBench.scala b/src/main/scala/vexriscv/demo/SynthesisBench.scala similarity index 99% rename from src/main/scala/VexRiscv/demo/SynthesisBench.scala rename to src/main/scala/vexriscv/demo/SynthesisBench.scala index 5bb2ad7..a78c2e5 100644 --- a/src/main/scala/VexRiscv/demo/SynthesisBench.scala +++ b/src/main/scala/vexriscv/demo/SynthesisBench.scala @@ -1,4 +1,4 @@ -package VexRiscv.demo +package vexriscv.demo import spinal.core.SpinalVerilog import spinal.lib.eda.bench.{XilinxStdTargets, Bench, AlteraStdTargets, Rtl} diff --git a/src/main/scala/VexRiscv/demo/VexRiscvAvalon.scala b/src/main/scala/vexriscv/demo/VexRiscvAvalon.scala similarity index 96% rename from src/main/scala/VexRiscv/demo/VexRiscvAvalon.scala rename to src/main/scala/vexriscv/demo/VexRiscvAvalon.scala index affefa1..8e9637c 100644 --- a/src/main/scala/VexRiscv/demo/VexRiscvAvalon.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAvalon.scala @@ -1,8 +1,8 @@ -package VexRiscv.demo +package vexriscv.demo -import VexRiscv.Plugin._ -import VexRiscv.{VexRiscv, Plugin, VexRiscvConfig} -import VexRiscv.ip.{DataCacheConfig, InstructionCacheConfig} +import vexriscv.plugin._ +import vexriscv.{VexRiscv, plugin, VexRiscvConfig} +import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba3.apb.Apb3 @@ -71,7 +71,7 @@ object VexRiscvAvalon{ catchIllegalInstruction = true ), new RegFilePlugin( - regFileReadyKind = Plugin.SYNC, + regFileReadyKind = plugin.SYNC, zeroBoot = false ), new IntAluPlugin, diff --git a/src/main/scala/VexRiscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala similarity index 99% rename from src/main/scala/VexRiscv/ip/DataCache.scala rename to src/main/scala/vexriscv/ip/DataCache.scala index af89f42..a76acb8 100644 --- a/src/main/scala/VexRiscv/ip/DataCache.scala +++ b/src/main/scala/vexriscv/ip/DataCache.scala @@ -1,6 +1,6 @@ -package VexRiscv.ip +package vexriscv.ip -import VexRiscv._ +import vexriscv._ import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba4.axi.{Axi4Shared, Axi4Config} diff --git a/src/main/scala/VexRiscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala similarity index 99% rename from src/main/scala/VexRiscv/ip/InstructionCache.scala rename to src/main/scala/vexriscv/ip/InstructionCache.scala index 813df19..eceec6f 100644 --- a/src/main/scala/VexRiscv/ip/InstructionCache.scala +++ b/src/main/scala/vexriscv/ip/InstructionCache.scala @@ -1,6 +1,6 @@ -package VexRiscv.ip +package vexriscv.ip -import VexRiscv._ +import vexriscv._ import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba4.axi.{Axi4ReadOnly, Axi4Config} diff --git a/src/main/scala/VexRiscv/Plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala similarity index 99% rename from src/main/scala/VexRiscv/Plugin/BranchPlugin.scala rename to src/main/scala/vexriscv/plugin/BranchPlugin.scala index c6fe12f..f6c0e39 100644 --- a/src/main/scala/VexRiscv/Plugin/BranchPlugin.scala +++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala @@ -1,7 +1,7 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv.Riscv._ -import VexRiscv._ +import vexriscv.Riscv._ +import vexriscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala similarity index 99% rename from src/main/scala/VexRiscv/Plugin/CsrPlugin.scala rename to src/main/scala/vexriscv/plugin/CsrPlugin.scala index 6edbc3e..0883ded 100644 --- a/src/main/scala/VexRiscv/Plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -1,9 +1,9 @@ -package VexRiscv.Plugin +package vexriscv.plugin import spinal.core._ import spinal.lib._ -import VexRiscv._ -import VexRiscv.Riscv._ +import vexriscv._ +import vexriscv.Riscv._ import scala.collection.mutable.ArrayBuffer import scala.collection.mutable diff --git a/src/main/scala/VexRiscv/Plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala similarity index 99% rename from src/main/scala/VexRiscv/Plugin/DBusCachedPlugin.scala rename to src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala index 463ba01..5e8157b 100644 --- a/src/main/scala/VexRiscv/Plugin/DBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala @@ -1,7 +1,7 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv.ip._ -import VexRiscv._ +import vexriscv.ip._ +import vexriscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala similarity index 99% rename from src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala rename to src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 0382018..713d554 100644 --- a/src/main/scala/VexRiscv/Plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv._ +import vexriscv._ import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba4.axi._ diff --git a/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala similarity index 84% rename from src/main/scala/VexRiscv/Plugin/DebugPlugin.scala rename to src/main/scala/vexriscv/plugin/DebugPlugin.scala index 0872c5d..a58e618 100644 --- a/src/main/scala/VexRiscv/Plugin/DebugPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala @@ -1,8 +1,10 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv.Plugin.IntAluPlugin.{AluCtrlEnum, ALU_CTRL} -import VexRiscv._ -import VexRiscv.ip._ +import spinal.lib.com.jtag.Jtag +import spinal.lib.system.debugger.{SystemDebugger, JtagBridge, SystemDebuggerConfig} +import vexriscv.plugin.IntAluPlugin.{AluCtrlEnum, ALU_CTRL} +import vexriscv._ +import vexriscv.ip._ import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba3.apb.{Apb3Config, Apb3} @@ -58,6 +60,26 @@ case class DebugExtensionBus() extends Bundle with IMasterSlave{ bus } + + def fromJtag(): Jtag ={ + val jtagConfig = SystemDebuggerConfig( + memAddressWidth = 32, + memDataWidth = 32, + remoteCmdWidth = 1 + ) + val jtagBridge = new JtagBridge(jtagConfig) + val debugger = new SystemDebugger(jtagConfig) + debugger.io.remote <> jtagBridge.io.remote + debugger.io.mem.cmd.valid <> cmd.valid + debugger.io.mem.cmd.ready <> cmd.ready + debugger.io.mem.cmd.wr <> cmd.wr + debugger.io.mem.cmd.address.resized <> cmd.address + debugger.io.mem.cmd.data <> cmd.data + debugger.io.mem.rsp.valid <> RegNext(cmd.fire).init(False) + debugger.io.mem.rsp.payload <> rsp.data + + jtagBridge.io.jtag + } } case class DebugExtensionIo() extends Bundle with IMasterSlave{ diff --git a/src/main/scala/VexRiscv/Plugin/DecoderSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala similarity index 99% rename from src/main/scala/VexRiscv/Plugin/DecoderSimplePlugin.scala rename to src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala index 73af9ab..cbcb5d5 100644 --- a/src/main/scala/VexRiscv/Plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv._ +import vexriscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/DivPlugin.scala b/src/main/scala/vexriscv/plugin/DivPlugin.scala similarity index 97% rename from src/main/scala/VexRiscv/Plugin/DivPlugin.scala rename to src/main/scala/vexriscv/plugin/DivPlugin.scala index a5601f3..1c0a795 100644 --- a/src/main/scala/VexRiscv/Plugin/DivPlugin.scala +++ b/src/main/scala/vexriscv/plugin/DivPlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv.{VexRiscv, _} +import vexriscv.{VexRiscv, _} import spinal.core._ import spinal.lib.math.MixedDivider diff --git a/src/main/scala/VexRiscv/Plugin/HazardPessimisticPlugin.scala b/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala similarity index 92% rename from src/main/scala/VexRiscv/Plugin/HazardPessimisticPlugin.scala rename to src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala index f688ff9..2470d21 100644 --- a/src/main/scala/VexRiscv/Plugin/HazardPessimisticPlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardPessimisticPlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv._ +import vexriscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/HazardSimplePlugin.scala b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala similarity index 98% rename from src/main/scala/VexRiscv/Plugin/HazardSimplePlugin.scala rename to src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala index 4e0feee..04b27f1 100644 --- a/src/main/scala/VexRiscv/Plugin/HazardSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/HazardSimplePlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv._ +import vexriscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/IBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala similarity index 98% rename from src/main/scala/VexRiscv/Plugin/IBusCachedPlugin.scala rename to src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala index a309706..69eb62f 100644 --- a/src/main/scala/VexRiscv/Plugin/IBusCachedPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusCachedPlugin.scala @@ -1,7 +1,7 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv._ -import VexRiscv.ip._ +import vexriscv._ +import vexriscv.ip._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala similarity index 98% rename from src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala rename to src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 19c93cc..1e89719 100644 --- a/src/main/scala/VexRiscv/Plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv.{Stageable, ExceptionService, ExceptionCause, VexRiscv} +import vexriscv.{Stageable, ExceptionService, ExceptionCause, VexRiscv} import spinal.core._ import spinal.lib._ import spinal.lib.bus.amba4.axi._ diff --git a/src/main/scala/VexRiscv/Plugin/IntAluPlugin.scala b/src/main/scala/vexriscv/plugin/IntAluPlugin.scala similarity index 99% rename from src/main/scala/VexRiscv/Plugin/IntAluPlugin.scala rename to src/main/scala/vexriscv/plugin/IntAluPlugin.scala index 5bd214f..2610aac 100644 --- a/src/main/scala/VexRiscv/Plugin/IntAluPlugin.scala +++ b/src/main/scala/vexriscv/plugin/IntAluPlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv._ +import vexriscv._ import spinal.core._ object IntAluPlugin{ object AluBitwiseCtrlEnum extends SpinalEnum(binarySequential){ diff --git a/src/main/scala/VexRiscv/Plugin/MemoryTranslatorPlugin.scala b/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala similarity index 99% rename from src/main/scala/VexRiscv/Plugin/MemoryTranslatorPlugin.scala rename to src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala index ce4370a..41d9bb7 100644 --- a/src/main/scala/VexRiscv/Plugin/MemoryTranslatorPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MemoryTranslatorPlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv.{VexRiscv, _} +import vexriscv.{VexRiscv, _} import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/MulPlugin.scala b/src/main/scala/vexriscv/plugin/MulPlugin.scala similarity index 97% rename from src/main/scala/VexRiscv/Plugin/MulPlugin.scala rename to src/main/scala/vexriscv/plugin/MulPlugin.scala index 339db86..6975911 100644 --- a/src/main/scala/VexRiscv/Plugin/MulPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulPlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin -import VexRiscv._ -import VexRiscv.VexRiscv +package vexriscv.plugin +import vexriscv._ +import vexriscv.VexRiscv import spinal.core._ class MulPlugin extends Plugin[VexRiscv]{ diff --git a/src/main/scala/VexRiscv/Plugin/PcManagerSimplePlugin.scala b/src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala similarity index 98% rename from src/main/scala/VexRiscv/Plugin/PcManagerSimplePlugin.scala rename to src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala index 22f9b06..5e9f881 100644 --- a/src/main/scala/VexRiscv/Plugin/PcManagerSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/PcManagerSimplePlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv._ +import vexriscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/Plugin.scala b/src/main/scala/vexriscv/plugin/Plugin.scala similarity index 90% rename from src/main/scala/VexRiscv/Plugin/Plugin.scala rename to src/main/scala/vexriscv/plugin/Plugin.scala index 3375757..cd440e0 100644 --- a/src/main/scala/VexRiscv/Plugin/Plugin.scala +++ b/src/main/scala/vexriscv/plugin/Plugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv.{Pipeline, Stage} +import vexriscv.{Pipeline, Stage} import spinal.core.Area /** diff --git a/src/main/scala/VexRiscv/Plugin/RegFilePlugin.scala b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala similarity index 98% rename from src/main/scala/VexRiscv/Plugin/RegFilePlugin.scala rename to src/main/scala/vexriscv/plugin/RegFilePlugin.scala index 6417dfa..4c481a0 100644 --- a/src/main/scala/VexRiscv/Plugin/RegFilePlugin.scala +++ b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv._ +import vexriscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/ShiftPlugins.scala b/src/main/scala/vexriscv/plugin/ShiftPlugins.scala similarity index 99% rename from src/main/scala/VexRiscv/Plugin/ShiftPlugins.scala rename to src/main/scala/vexriscv/plugin/ShiftPlugins.scala index 81663fa..fdce39c 100644 --- a/src/main/scala/VexRiscv/Plugin/ShiftPlugins.scala +++ b/src/main/scala/vexriscv/plugin/ShiftPlugins.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv._ +import vexriscv._ import spinal.core._ import spinal.lib.Reverse diff --git a/src/main/scala/VexRiscv/Plugin/SingleInstructionLimiterPlugin.scala b/src/main/scala/vexriscv/plugin/SingleInstructionLimiterPlugin.scala similarity index 88% rename from src/main/scala/VexRiscv/Plugin/SingleInstructionLimiterPlugin.scala rename to src/main/scala/vexriscv/plugin/SingleInstructionLimiterPlugin.scala index 62208fb..48c22d7 100644 --- a/src/main/scala/VexRiscv/Plugin/SingleInstructionLimiterPlugin.scala +++ b/src/main/scala/vexriscv/plugin/SingleInstructionLimiterPlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv._ +import vexriscv._ import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/SrcPlugin.scala b/src/main/scala/vexriscv/plugin/SrcPlugin.scala similarity index 97% rename from src/main/scala/VexRiscv/Plugin/SrcPlugin.scala rename to src/main/scala/vexriscv/plugin/SrcPlugin.scala index d967e0c..35bc203 100644 --- a/src/main/scala/VexRiscv/Plugin/SrcPlugin.scala +++ b/src/main/scala/vexriscv/plugin/SrcPlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv.{Riscv, VexRiscv} +import vexriscv.{Riscv, VexRiscv} import spinal.core._ diff --git a/src/main/scala/VexRiscv/Plugin/StaticMemoryTranslatorPlugin.scala b/src/main/scala/vexriscv/plugin/StaticMemoryTranslatorPlugin.scala similarity index 95% rename from src/main/scala/VexRiscv/Plugin/StaticMemoryTranslatorPlugin.scala rename to src/main/scala/vexriscv/plugin/StaticMemoryTranslatorPlugin.scala index 05aa6cd..a4e96e0 100644 --- a/src/main/scala/VexRiscv/Plugin/StaticMemoryTranslatorPlugin.scala +++ b/src/main/scala/vexriscv/plugin/StaticMemoryTranslatorPlugin.scala @@ -1,6 +1,6 @@ -package VexRiscv.Plugin +package vexriscv.plugin -import VexRiscv.{VexRiscv, _} +import vexriscv.{VexRiscv, _} import spinal.core._ import spinal.lib._ diff --git a/src/main/scala/VexRiscv/Plugin/YamlPlugin.scala b/src/main/scala/vexriscv/plugin/YamlPlugin.scala similarity index 91% rename from src/main/scala/VexRiscv/Plugin/YamlPlugin.scala rename to src/main/scala/vexriscv/plugin/YamlPlugin.scala index 121a08f..ca53e42 100644 --- a/src/main/scala/VexRiscv/Plugin/YamlPlugin.scala +++ b/src/main/scala/vexriscv/plugin/YamlPlugin.scala @@ -1,8 +1,8 @@ -package VexRiscv.Plugin +package vexriscv.plugin import java.util -import VexRiscv.{ReportService, VexRiscv} +import vexriscv.{ReportService, VexRiscv} import org.yaml.snakeyaml.{DumperOptions, Yaml}