diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
index 8005440..d685a34 100644
--- a/src/main/scala/vexriscv/ip/DataCache.scala
+++ b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -514,6 +514,7 @@ class DataCache(val p : DataCacheConfig) extends Component{
     val counter = Reg(UInt(log2Up(pendingMax) + 1 bits)) init(0)
     counter := counter + U(io.mem.cmd.fire && io.mem.cmd.last) - U(io.mem.rsp.valid  && io.mem.rsp.last)
 
+    val consistent = counter === 0
     val full = RegNext(counter.msb)
     val last = counter === 1
 
@@ -533,6 +534,8 @@ class DataCache(val p : DataCacheConfig) extends Component{
 
     val full = RegNext(counter.msb)
     io.cpu.execute.haltIt setWhen(full)
+
+    val consistent = counter === 0
   }
 
 
@@ -546,9 +549,9 @@ class DataCache(val p : DataCacheConfig) extends Component{
     val wayInvalidate = B(0, wayCount bits) //Used if invalidate enabled
 
     when(io.cpu.execute.fence){
-      val counter = if(withInvalidate) sync.counter else if(withWriteResponse) pending.counter else null
-      if(counter != null){
-        when(counter =/= 0 || io.cpu.memory.isValid || io.cpu.writeBack.isValid){
+      val consistent = if(withInvalidate) sync.consistent else if(withWriteResponse) pending.consistent else null
+      if(consistent != null){
+        when(!consistent || io.cpu.memory.isValid && io.cpu.memory.isWrite || io.cpu.writeBack.isValid && io.cpu.memory.isWrite){
           io.cpu.execute.haltIt := True
         }
       }
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index abd6d52..769ed07 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -229,11 +229,10 @@ class DBusCachedPlugin(val config : DataCacheConfig,
         val ff = input(INSTRUCTION)(31 downto 20).as(FenceFlags())
         if(withWriteResponse){
           hazard setWhen(input(MEMORY_FENCE) && (ff.PS && ff.SL)) //Manage write to read hit ordering (ensure invalidation timings)
-//          Not required as LR SC AMO emited on the memory bus enforce the ordering, + it bypass the cache
-//          when(input(INSTRUCTION)(26 downto 25) =/= 0){
-//            if(withLrSc) hazard setWhen(input(MEMORY_LRSC))
-//            if(withAmo)  hazard setWhen(input(MEMORY_AMO))
-//          }
+          when(input(INSTRUCTION)(26 downto 25) =/= 0){
+            if(withLrSc) hazard setWhen(input(MEMORY_LRSC))
+            if(withAmo)  hazard setWhen(input(MEMORY_AMO))
+          }
         }
         insert(MEMORY_FENCE_DECODED) := hazard
       }