diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
index 03131c1..d17e4fb 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -193,6 +193,31 @@ object VexRiscvSmpClusterGen {
     assert(dCacheSize/dCacheWays <= 4096, "Data cache ways can't be bigger than 4096 bytes")
     assert(!(withDouble && !withFloat))
 
+    val csrConfig = if(withSupervisor){
+      CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY)
+    } else {
+      CsrPluginConfig(
+        catchIllegalAccess = true,
+        mvendorid      = null,
+        marchid        = null,
+        mimpid         = null,
+        mhartid        = 0,
+        misaExtensionsInit = 0,
+        misaAccess     = CsrAccess.NONE,
+        mtvecAccess    = CsrAccess.READ_WRITE,
+        mtvecInit      = null,
+        mepcAccess     = CsrAccess.READ_WRITE,
+        mscratchGen    = false,
+        mcauseAccess   = CsrAccess.READ_ONLY,
+        mbadaddrAccess = CsrAccess.READ_ONLY,
+        mcycleAccess   = CsrAccess.NONE,
+        minstretAccess = CsrAccess.NONE,
+        ecallGen       = true,
+        wfiGenAsWait   = false,
+        wfiGenAsNop    = true,
+        ucycleAccess   = CsrAccess.NONE
+      )
+    }
     val config = VexRiscvConfig(
       plugins = List(
         if(withMmu)new MmuPlugin(
@@ -290,7 +315,7 @@ object VexRiscvSmpClusterGen {
           mulUnrollFactor = 32,
           divUnrollFactor = 1
         ),
-        new CsrPlugin(CsrPluginConfig.openSbi(mhartid = hartId, misa = Riscv.misaToInt(s"ima${if(withFloat) "f" else ""}${if(withDouble) "d" else ""}s")).copy(utimeAccess = CsrAccess.READ_ONLY)),
+        new CsrPlugin(csrConfig),
         new BranchPlugin(
           earlyBranch = earlyBranch,
           catchAddressMisaligned = true,