From a6dc53044140971f1427c451f159fcea61931784 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Tue, 9 Apr 2019 19:27:42 +0200 Subject: [PATCH] Added lrsc/amo tests --- src/test/cpp/raw/amo/.gitignore | 4 + src/test/cpp/raw/amo/build/amo.asm | 247 +++++++++++++++++++++++++ src/test/cpp/raw/amo/build/amo.hex | 45 +++++ src/test/cpp/raw/amo/makefile | 5 + src/test/cpp/raw/amo/src/crt.S | 174 ++++++++++++++++++ src/test/cpp/raw/amo/src/ld | 16 ++ src/test/cpp/raw/common/asm.mk | 5 +- src/test/cpp/raw/lrsc/.gitignore | 4 + src/test/cpp/raw/lrsc/build/lrsc.asm | 217 ++++++++++++++++++++++ src/test/cpp/raw/lrsc/build/lrsc.hex | 53 ++++++ src/test/cpp/raw/lrsc/makefile | 5 + src/test/cpp/raw/lrsc/src/crt.S | 265 +++++++++++++++++++++++++++ src/test/cpp/raw/lrsc/src/ld | 16 ++ src/test/cpp/regression/main.cpp | 8 +- src/test/cpp/regression/makefile | 6 +- 15 files changed, 1064 insertions(+), 6 deletions(-) create mode 100644 src/test/cpp/raw/amo/.gitignore create mode 100644 src/test/cpp/raw/amo/build/amo.asm create mode 100644 src/test/cpp/raw/amo/build/amo.hex create mode 100644 src/test/cpp/raw/amo/makefile create mode 100644 src/test/cpp/raw/amo/src/crt.S create mode 100644 src/test/cpp/raw/amo/src/ld create mode 100644 src/test/cpp/raw/lrsc/.gitignore create mode 100644 src/test/cpp/raw/lrsc/build/lrsc.asm create mode 100644 src/test/cpp/raw/lrsc/build/lrsc.hex create mode 100644 src/test/cpp/raw/lrsc/makefile create mode 100644 src/test/cpp/raw/lrsc/src/crt.S create mode 100644 src/test/cpp/raw/lrsc/src/ld diff --git a/src/test/cpp/raw/amo/.gitignore b/src/test/cpp/raw/amo/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/src/test/cpp/raw/amo/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o \ No newline at end of file diff --git a/src/test/cpp/raw/amo/build/amo.asm b/src/test/cpp/raw/amo/build/amo.asm new file mode 100644 index 0000000..d86b61c --- /dev/null +++ b/src/test/cpp/raw/amo/build/amo.asm @@ -0,0 +1,247 @@ + +build/amo.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00100e13 li t3,1 +80000004: 00000097 auipc ra,0x0 +80000008: 27408093 addi ra,ra,628 # 80000278 +8000000c: 02d00113 li sp,45 +80000010: 0820a1af amoswap.w gp,sp,(ra) +80000014: 0000a203 lw tp,0(ra) +80000018: 02d00a13 li s4,45 +8000001c: 224a1663 bne s4,tp,80000248 +80000020: 00b00a13 li s4,11 +80000024: 223a1263 bne s4,gp,80000248 + +80000028 : +80000028: 00200e13 li t3,2 +8000002c: 00000097 auipc ra,0x0 +80000030: 25008093 addi ra,ra,592 # 8000027c +80000034: 03700113 li sp,55 +80000038: 0820a1af amoswap.w gp,sp,(ra) +8000003c: 0000a203 lw tp,0(ra) +80000040: 03700a13 li s4,55 +80000044: 204a1263 bne s4,tp,80000248 +80000048: 01600a13 li s4,22 +8000004c: 1e3a1e63 bne s4,gp,80000248 + +80000050 : +80000050: 00300e13 li t3,3 +80000054: 00000097 auipc ra,0x0 +80000058: 22c08093 addi ra,ra,556 # 80000280 +8000005c: 04200113 li sp,66 +80000060: 0020a1af amoadd.w gp,sp,(ra) +80000064: 0000a203 lw tp,0(ra) +80000068: 08b00a13 li s4,139 +8000006c: 1c4a1e63 bne s4,tp,80000248 +80000070: 04900a13 li s4,73 +80000074: 1c3a1a63 bne s4,gp,80000248 + +80000078 : +80000078: 00400e13 li t3,4 +8000007c: 00000097 auipc ra,0x0 +80000080: 20808093 addi ra,ra,520 # 80000284 +80000084: 05700113 li sp,87 +80000088: 2020a1af amoxor.w gp,sp,(ra) +8000008c: 0000a203 lw tp,0(ra) +80000090: 06d00a13 li s4,109 +80000094: 1a4a1a63 bne s4,tp,80000248 +80000098: 03a00a13 li s4,58 +8000009c: 1a3a1663 bne s4,gp,80000248 + +800000a0 : +800000a0: 00500e13 li t3,5 +800000a4: 00000097 auipc ra,0x0 +800000a8: 1e408093 addi ra,ra,484 # 80000288 +800000ac: 02c00113 li sp,44 +800000b0: 6020a1af amoand.w gp,sp,(ra) +800000b4: 0000a203 lw tp,0(ra) +800000b8: 02800a13 li s4,40 +800000bc: 184a1663 bne s4,tp,80000248 +800000c0: 03800a13 li s4,56 +800000c4: 183a1263 bne s4,gp,80000248 + +800000c8 : +800000c8: 00600e13 li t3,6 +800000cc: 00000097 auipc ra,0x0 +800000d0: 1c008093 addi ra,ra,448 # 8000028c +800000d4: 01800113 li sp,24 +800000d8: 4020a1af amoor.w gp,sp,(ra) +800000dc: 0000a203 lw tp,0(ra) +800000e0: 05b00a13 li s4,91 +800000e4: 164a1263 bne s4,tp,80000248 +800000e8: 04b00a13 li s4,75 +800000ec: 143a1e63 bne s4,gp,80000248 + +800000f0 : +800000f0: 00700e13 li t3,7 +800000f4: 00000097 auipc ra,0x0 +800000f8: 19c08093 addi ra,ra,412 # 80000290 +800000fc: 01800113 li sp,24 +80000100: 8020a1af amomin.w gp,sp,(ra) +80000104: 0000a203 lw tp,0(ra) +80000108: 01800a13 li s4,24 +8000010c: 124a1e63 bne s4,tp,80000248 +80000110: 03800a13 li s4,56 +80000114: 123a1a63 bne s4,gp,80000248 + +80000118 : +80000118: 00800e13 li t3,8 +8000011c: 00000097 auipc ra,0x0 +80000120: 17808093 addi ra,ra,376 # 80000294 +80000124: 05800113 li sp,88 +80000128: 8020a1af amomin.w gp,sp,(ra) +8000012c: 0000a203 lw tp,0(ra) +80000130: 05300a13 li s4,83 +80000134: 104a1a63 bne s4,tp,80000248 +80000138: 05300a13 li s4,83 +8000013c: 103a1663 bne s4,gp,80000248 + +80000140 : +80000140: 00900e13 li t3,9 +80000144: 00000097 auipc ra,0x0 +80000148: 15408093 addi ra,ra,340 # 80000298 +8000014c: fca00113 li sp,-54 +80000150: 8020a1af amomin.w gp,sp,(ra) +80000154: 0000a203 lw tp,0(ra) +80000158: fca00a13 li s4,-54 +8000015c: 0e4a1663 bne s4,tp,80000248 +80000160: 02100a13 li s4,33 +80000164: 0e3a1263 bne s4,gp,80000248 + +80000168 : +80000168: 00a00e13 li t3,10 +8000016c: 00000097 auipc ra,0x0 +80000170: 13008093 addi ra,ra,304 # 8000029c +80000174: 03400113 li sp,52 +80000178: 8020a1af amomin.w gp,sp,(ra) +8000017c: 0000a203 lw tp,0(ra) +80000180: fbf00a13 li s4,-65 +80000184: 0c4a1263 bne s4,tp,80000248 +80000188: fbf00a13 li s4,-65 +8000018c: 0a3a1e63 bne s4,gp,80000248 + +80000190 : +80000190: 00b00e13 li t3,11 +80000194: 00000097 auipc ra,0x0 +80000198: 10c08093 addi ra,ra,268 # 800002a0 +8000019c: fcc00113 li sp,-52 +800001a0: a020a1af amomax.w gp,sp,(ra) +800001a4: 0000a203 lw tp,0(ra) +800001a8: fcc00a13 li s4,-52 +800001ac: 084a1e63 bne s4,tp,80000248 +800001b0: fa900a13 li s4,-87 +800001b4: 083a1a63 bne s4,gp,80000248 + +800001b8 : +800001b8: 00c00e13 li t3,12 +800001bc: 00000097 auipc ra,0x0 +800001c0: 0e808093 addi ra,ra,232 # 800002a4 +800001c4: 03400113 li sp,52 +800001c8: a020a1af amomax.w gp,sp,(ra) +800001cc: 0000a203 lw tp,0(ra) +800001d0: 03400a13 li s4,52 +800001d4: 064a1a63 bne s4,tp,80000248 +800001d8: fc900a13 li s4,-55 +800001dc: 063a1663 bne s4,gp,80000248 + +800001e0 : +800001e0: 00d00e13 li t3,13 +800001e4: 00000097 auipc ra,0x0 +800001e8: 0c408093 addi ra,ra,196 # 800002a8 +800001ec: ffff0137 lui sp,0xffff0 +800001f0: c020a1af amominu.w gp,sp,(ra) +800001f4: 0000a203 lw tp,0(ra) +800001f8: ffff0a37 lui s4,0xffff0 +800001fc: 044a1663 bne s4,tp,80000248 +80000200: ffff0a37 lui s4,0xffff0 +80000204: 004a0a13 addi s4,s4,4 # ffff0004 +80000208: 043a1063 bne s4,gp,80000248 +8000020c: 0480006f j 80000254 + +80000210 : +80000210: 00e00e13 li t3,14 +80000214: 00000097 auipc ra,0x0 +80000218: 09808093 addi ra,ra,152 # 800002ac +8000021c: ffff0137 lui sp,0xffff0 +80000220: 00c10113 addi sp,sp,12 # ffff000c +80000224: e020a1af amomaxu.w gp,sp,(ra) +80000228: 0000a203 lw tp,0(ra) +8000022c: ffff0a37 lui s4,0xffff0 +80000230: 00ca0a13 addi s4,s4,12 # ffff000c +80000234: 004a1a63 bne s4,tp,80000248 +80000238: ffff0a37 lui s4,0xffff0 +8000023c: 005a0a13 addi s4,s4,5 # ffff0005 +80000240: 003a1463 bne s4,gp,80000248 +80000244: 0100006f j 80000254 + +80000248 : +80000248: f0100137 lui sp,0xf0100 +8000024c: f2410113 addi sp,sp,-220 # f00fff24 +80000250: 01c12023 sw t3,0(sp) + +80000254 : +80000254: f0100137 lui sp,0xf0100 +80000258: f2010113 addi sp,sp,-224 # f00fff20 +8000025c: 00012023 sw zero,0(sp) +80000260: 00000013 nop +80000264: 00000013 nop +80000268: 00000013 nop +8000026c: 00000013 nop +80000270: 00000013 nop +80000274: 00000013 nop + +80000278 : +80000278: 0000000b 0xb + +8000027c : +8000027c: 0016 c.slli zero,0x5 + ... + +80000280 : +80000280: 0049 c.nop 18 + ... + +80000284 : +80000284: 003a c.slli zero,0xe + ... + +80000288 : +80000288: 0038 addi a4,sp,8 + ... + +8000028c : +8000028c: 0000004b fnmsub.s ft0,ft0,ft0,ft0,rne + +80000290 : +80000290: 0038 addi a4,sp,8 + ... + +80000294 : +80000294: 00000053 fadd.s ft0,ft0,ft0,rne + +80000298 : +80000298: 0021 c.nop 8 + ... + +8000029c : +8000029c: ffffffbf 0xffffffbf + +800002a0 : +800002a0: ffa9 bnez a5,800001fa +800002a2: ffff 0xffff + +800002a4 : +800002a4: ffc9 bnez a5,8000023e +800002a6: ffff 0xffff + +800002a8 : +800002a8: 0004 0x4 +800002aa: ffff 0xffff + +800002ac : +800002ac: 0005 c.nop 1 +800002ae: ffff 0xffff diff --git a/src/test/cpp/raw/amo/build/amo.hex b/src/test/cpp/raw/amo/build/amo.hex new file mode 100644 index 0000000..74d3567 --- /dev/null +++ b/src/test/cpp/raw/amo/build/amo.hex @@ -0,0 +1,45 @@ +:0200000480007A +:10000000130E100097000000938040271301D002C8 +:10001000AFA1200803A20000130AD00263164A22EF +:10002000130AB00063123A22130E2000970000005A +:100030009380002513017003AFA1200803A20000E4 +:10004000130A700363124A20130A6001631E3A1EEA +:10005000130E3000970000009380C022130120048B +:10006000AFA1200003A20000130AB008631E4A1CBF +:10007000130A9004631A3A1C130E40009700000004 +:100080009380802013017005AFA1202003A20000FF +:10009000130AD006631A4A1A130AA00363163A1AFF +:1000A000130E5000970000009380401E1301C00201 +:1000B000AFA1206003A20000130A800263164A1851 +:1000C000130A800363123A18130E600097000000B1 +:1000D0009380001C13018001AFA1204003A2000007 +:1000E000130AB00563124A16130AB004631E3A14C9 +:1000F000130E7000970000009380C0191301800157 +:10010000AFA1208003A20000130A8001631E4A12DF +:10011000130A8003631A3A12130E8000970000003E +:100120009380801713018005AFA1208003A20000F7 +:10013000130A3005631A4A10130A300563163A1081 +:10014000130E900097000000938040151301A0FC4F +:10015000AFA1208003A20000130AA0FC63164A0E80 +:10016000130A100263123A0E130EA000970000004B +:100170009380001313014003AFA1208003A200006D +:10018000130AF0FB63124A0C130AF0FB631E3A0ACF +:10019000130EB000970000009380C0101301C0FC44 +:1001A000AFA120A003A20000130AC0FC631E4A08EE +:1001B000130A90FA631A3A08130EC0009700000061 +:1001C0009380800E13014003AFA120A003A2000082 +:1001D000130A4003631A4A06130A90FC63163A0690 +:1001E000130ED000970000009380400C3701FFFFF2 +:1001F000AFA120C003A20000370AFFFF63164A0424 +:10020000370AFFFF130A4A0063103A046F008004A4 +:10021000130EE00097000000938080093701FFFF74 +:100220001301C100AFA120E003A20000370AFFFFC5 +:10023000130ACA00631A4A00370AFFFF130A5A005A +:1002400063143A006F000001370110F0130141F20E +:100250002320C101370110F0130101F22320010016 +:100260001300000013000000130000001300000042 +:1002700013000000130000000B0000001600000037 +:10028000490000003A000000380000004B00000068 +:10029000380000005300000021000000BFFFFFFFF6 +:1002A000A9FFFFFFC9FFFFFF0400FFFF0500FFFFDD +:00000001FF diff --git a/src/test/cpp/raw/amo/makefile b/src/test/cpp/raw/amo/makefile new file mode 100644 index 0000000..6e9afc5 --- /dev/null +++ b/src/test/cpp/raw/amo/makefile @@ -0,0 +1,5 @@ +PROJ_NAME=amo + +ATOMIC=yes + +include ../common/asm.mk \ No newline at end of file diff --git a/src/test/cpp/raw/amo/src/crt.S b/src/test/cpp/raw/amo/src/crt.S new file mode 100644 index 0000000..5696f1d --- /dev/null +++ b/src/test/cpp/raw/amo/src/crt.S @@ -0,0 +1,174 @@ +.globl _star +#define TEST_ID x28 + +_start: + +#define assert(reg, value) \ + li x20, value; \ + bne x20, reg, fail; + +test1: + li TEST_ID, 1 + la x1, test1_data + li x2, 45 + amoswap.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 45) + assert(x3, 11) + +test2: + li TEST_ID, 2 + la x1, test2_data + li x2, 55 + amoswap.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 55) + assert(x3, 22) + + +test3: + li TEST_ID,3 + la x1, test3_data + li x2, 66 + amoadd.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 66+73) + assert(x3, 73) + +test4: + li TEST_ID,4 + la x1, test4_data + li x2, 87 + amoxor.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 87^58) + assert(x3, 58) + +test5: + li TEST_ID,5 + la x1, test5_data + li x2, 44 + amoand.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 44 & 56) + assert(x3, 56) + +test6: + li TEST_ID,6 + la x1, test6_data + li x2, 24 + amoor.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 24 | 75) + assert(x3, 75) + +test7: + li TEST_ID,7 + la x1, test7_data + li x2, 24 + amomin.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 24) + assert(x3, 56) + + +test8: + li TEST_ID,8 + la x1, test8_data + li x2, 88 + amomin.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 83) + assert(x3, 83) + +test9: + li TEST_ID,9 + la x1, test9_data + li x2, -54 + amomin.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, -54) + assert(x3, 33) + +test10: + li TEST_ID,10 + la x1, test10_data + li x2, 52 + amomin.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, -65) + assert(x3, -65) + +test11: + li TEST_ID,11 + la x1, test11_data + li x2, -52 + amomax.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, -52) + assert(x3, -87) + +test12: + li TEST_ID,12 + la x1, test12_data + li x2, 52 + amomax.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 52) + assert(x3, -55) + + +test13: + li TEST_ID,13 + la x1, test13_data + li x2, 0xFFFF0000 + amominu.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 0xFFFF0000) + assert(x3, 0xFFFF0004) + + j pass + + +test14: + li TEST_ID,14 + la x1, test14_data + li x2, 0xFFFF000C + amomaxu.w x3,x2,(x1) + lw x4, 0(x1) + assert(x4, 0xFFFF000C) + assert(x3, 0xFFFF0005) + + j pass + + +fail: + li x2, 0xF00FFF24 + sw TEST_ID, 0(x2) + +pass: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + nop + nop + nop + nop + nop + nop + + +test1_data: .word 11 +test2_data: .word 22 +test3_data: .word 73 +test4_data: .word 58 +test5_data: .word 56 +test6_data: .word 75 +test7_data: .word 56 +test8_data: .word 83 +test9_data: .word 33 +test10_data: .word -65 +test11_data: .word -87 +test12_data: .word -55 +test13_data: .word 0xFFFF0004 +test14_data: .word 0xFFFF0005 \ No newline at end of file diff --git a/src/test/cpp/raw/amo/src/ld b/src/test/cpp/raw/amo/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/src/test/cpp/raw/amo/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/src/test/cpp/raw/common/asm.mk b/src/test/cpp/raw/common/asm.mk index f16774d..3d4b205 100644 --- a/src/test/cpp/raw/common/asm.mk +++ b/src/test/cpp/raw/common/asm.mk @@ -12,8 +12,11 @@ MARCH := rv32i ifeq ($(MULDIV),yes) MARCH := $(MARCH)m endif +ifeq ($(ATOMIC),yes) + MARCH := $(MARCH)a +endif ifeq ($(COMPRESSED),yes) - MARCH := $(MARCH)ac + MARCH := $(MARCH)c endif CFLAGS += -march=$(MARCH) -mabi=$(MABI) diff --git a/src/test/cpp/raw/lrsc/.gitignore b/src/test/cpp/raw/lrsc/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/src/test/cpp/raw/lrsc/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o \ No newline at end of file diff --git a/src/test/cpp/raw/lrsc/build/lrsc.asm b/src/test/cpp/raw/lrsc/build/lrsc.asm new file mode 100644 index 0000000..95b4751 --- /dev/null +++ b/src/test/cpp/raw/lrsc/build/lrsc.asm @@ -0,0 +1,217 @@ + +build/lrsc.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 : +80000000: 04c0006f j 8000004c <_start> +80000004: 00000013 nop +80000008: 00000013 nop +8000000c: 00000013 nop +80000010: 00000013 nop +80000014: 00000013 nop +80000018: 00000013 nop +8000001c: 00000013 nop + +80000020 : +80000020: 30002ef3 csrr t4,mstatus +80000024: 080efe93 andi t4,t4,128 +80000028: 000e8a63 beqz t4,8000003c +8000002c: 00002eb7 lui t4,0x2 +80000030: 800e8e93 addi t4,t4,-2048 # 1800 +80000034: 300e9073 csrw mstatus,t4 +80000038: 30200073 mret + +8000003c : +8000003c: 34102ef3 csrr t4,mepc +80000040: 004e8e93 addi t4,t4,4 +80000044: 341e9073 csrw mepc,t4 +80000048: 30200073 mret + +8000004c <_start>: +8000004c: 00100e13 li t3,1 +80000050: 10000537 lui a0,0x10000 +80000054: 06400593 li a1,100 +80000058: 06500613 li a2,101 +8000005c: 06600693 li a3,102 +80000060: 00d52023 sw a3,0(a0) # 10000000 +80000064: 18b5262f sc.w a2,a1,(a0) +80000068: 00100713 li a4,1 +8000006c: 26e61e63 bne a2,a4,800002e8 +80000070: 00052703 lw a4,0(a0) +80000074: 26e69a63 bne a3,a4,800002e8 +80000078: 00200e13 li t3,2 +8000007c: 10000537 lui a0,0x10000 +80000080: 00450513 addi a0,a0,4 # 10000004 +80000084: 06700593 li a1,103 +80000088: 06800613 li a2,104 +8000008c: 06900693 li a3,105 +80000090: 00d52023 sw a3,0(a0) +80000094: 18b5262f sc.w a2,a1,(a0) +80000098: 00100713 li a4,1 +8000009c: 24e61663 bne a2,a4,800002e8 +800000a0: 00052703 lw a4,0(a0) +800000a4: 24e69263 bne a3,a4,800002e8 +800000a8: 00300e13 li t3,3 +800000ac: 10000537 lui a0,0x10000 +800000b0: 00450513 addi a0,a0,4 # 10000004 +800000b4: 06700593 li a1,103 +800000b8: 06800613 li a2,104 +800000bc: 06900693 li a3,105 +800000c0: 18b5262f sc.w a2,a1,(a0) +800000c4: 00100713 li a4,1 +800000c8: 22e61063 bne a2,a4,800002e8 +800000cc: 00052703 lw a4,0(a0) +800000d0: 20e69c63 bne a3,a4,800002e8 +800000d4: 00400e13 li t3,4 +800000d8: 10000537 lui a0,0x10000 +800000dc: 00850513 addi a0,a0,8 # 10000008 +800000e0: 06a00593 li a1,106 +800000e4: 06b00613 li a2,107 +800000e8: 06c00693 li a3,108 +800000ec: 00d52023 sw a3,0(a0) +800000f0: 100527af lr.w a5,(a0) +800000f4: 18b5262f sc.w a2,a1,(a0) +800000f8: 1ed79863 bne a5,a3,800002e8 +800000fc: 1e061663 bnez a2,800002e8 +80000100: 00052703 lw a4,0(a0) +80000104: 1ee59263 bne a1,a4,800002e8 +80000108: 00500e13 li t3,5 +8000010c: 10000537 lui a0,0x10000 +80000110: 00850513 addi a0,a0,8 # 10000008 +80000114: 06d00593 li a1,109 +80000118: 06e00613 li a2,110 +8000011c: 06f00693 li a3,111 +80000120: 00d52023 sw a3,0(a0) +80000124: 18b5262f sc.w a2,a1,(a0) +80000128: 1c061063 bnez a2,800002e8 +8000012c: 00052703 lw a4,0(a0) +80000130: 1ae59c63 bne a1,a4,800002e8 +80000134: 00600e13 li t3,6 +80000138: 10000537 lui a0,0x10000 +8000013c: 00c50513 addi a0,a0,12 # 1000000c +80000140: 07000593 li a1,112 +80000144: 07100613 li a2,113 +80000148: 07200693 li a3,114 +8000014c: 10000437 lui s0,0x10000 +80000150: 01040413 addi s0,s0,16 # 10000010 +80000154: 07300493 li s1,115 +80000158: 07400913 li s2,116 +8000015c: 07500993 li s3,117 +80000160: 00d52023 sw a3,0(a0) +80000164: 01342023 sw s3,0(s0) +80000168: 100527af lr.w a5,(a0) +8000016c: 10042aaf lr.w s5,(s0) +80000170: 18b5262f sc.w a2,a1,(a0) +80000174: 1894292f sc.w s2,s1,(s0) +80000178: 16d79863 bne a5,a3,800002e8 +8000017c: 16061663 bnez a2,800002e8 +80000180: 00052703 lw a4,0(a0) +80000184: 16e59263 bne a1,a4,800002e8 +80000188: 173a9063 bne s5,s3,800002e8 +8000018c: 14091e63 bnez s2,800002e8 +80000190: 00042a03 lw s4,0(s0) +80000194: 15449a63 bne s1,s4,800002e8 +80000198: 00700e13 li t3,7 +8000019c: 10000537 lui a0,0x10000 +800001a0: 01450513 addi a0,a0,20 # 10000014 +800001a4: 07800593 li a1,120 +800001a8: 07900613 li a2,121 +800001ac: 07a00693 li a3,122 +800001b0: 01000e93 li t4,16 + +800001b4 : +800001b4: 00d52023 sw a3,0(a0) +800001b8: 100527af lr.w a5,(a0) +800001bc: 18b5262f sc.w a2,a1,(a0) +800001c0: 12d79463 bne a5,a3,800002e8 +800001c4: 12061263 bnez a2,800002e8 +800001c8: 00052703 lw a4,0(a0) +800001cc: 10e59e63 bne a1,a4,800002e8 +800001d0: fffe8e93 addi t4,t4,-1 +800001d4: 00450513 addi a0,a0,4 +800001d8: 00358593 addi a1,a1,3 +800001dc: 00360613 addi a2,a2,3 +800001e0: 00368693 addi a3,a3,3 +800001e4: fc0e98e3 bnez t4,800001b4 +800001e8: 00900e13 li t3,9 +800001ec: 10000537 lui a0,0x10000 +800001f0: 10050513 addi a0,a0,256 # 10000100 +800001f4: 07b00593 li a1,123 +800001f8: 07c00613 li a2,124 +800001fc: 07d00693 li a3,125 +80000200: 00d52023 sw a3,0(a0) +80000204: 100527af lr.w a5,(a0) +80000208: 00000073 ecall +8000020c: 18b5262f sc.w a2,a1,(a0) +80000210: 00100713 li a4,1 +80000214: 0ce61a63 bne a2,a4,800002e8 +80000218: 00052703 lw a4,0(a0) +8000021c: 0ce69663 bne a3,a4,800002e8 +80000220: 00b00e13 li t3,11 +80000224: 10000537 lui a0,0x10000 +80000228: 30050513 addi a0,a0,768 # 10000300 +8000022c: 08200593 li a1,130 +80000230: 08300613 li a2,131 +80000234: 08400693 li a3,132 +80000238: 00d52023 sw a3,0(a0) +8000023c: 00001eb7 lui t4,0x1 +80000240: 800e8e93 addi t4,t4,-2048 # 800 +80000244: 304e9073 csrw mie,t4 +80000248: 00800e93 li t4,8 +8000024c: 100527af lr.w a5,(a0) +80000250: 300e9073 csrw mstatus,t4 +80000254: 00000013 nop +80000258: 00000013 nop +8000025c: 00000013 nop +80000260: 00000013 nop +80000264: 00000013 nop +80000268: 00000013 nop +8000026c: 18b5262f sc.w a2,a1,(a0) +80000270: 00100713 li a4,1 +80000274: 06e61a63 bne a2,a4,800002e8 +80000278: 00052703 lw a4,0(a0) +8000027c: 06e69663 bne a3,a4,800002e8 +80000280: 00c00e13 li t3,12 +80000284: 10000537 lui a0,0x10000 +80000288: 40050513 addi a0,a0,1024 # 10000400 +8000028c: 08c00593 li a1,140 +80000290: 08d00613 li a2,141 +80000294: 08e00693 li a3,142 +80000298: 00d52023 sw a3,0(a0) +8000029c: 00001eb7 lui t4,0x1 +800002a0: 800e8e93 addi t4,t4,-2048 # 800 +800002a4: 304e9073 csrw mie,t4 +800002a8: 00002eb7 lui t4,0x2 +800002ac: 808e8e93 addi t4,t4,-2040 # 1808 +800002b0: 100527af lr.w a5,(a0) +800002b4: 300e9073 csrw mstatus,t4 +800002b8: 00000013 nop +800002bc: 00000013 nop +800002c0: 00000013 nop +800002c4: 00000013 nop +800002c8: 00000013 nop +800002cc: 00000013 nop +800002d0: 18b5262f sc.w a2,a1,(a0) +800002d4: 00100713 li a4,1 +800002d8: 00e61863 bne a2,a4,800002e8 +800002dc: 00052703 lw a4,0(a0) +800002e0: 00e69463 bne a3,a4,800002e8 +800002e4: 0100006f j 800002f4 + +800002e8 : +800002e8: f0100137 lui sp,0xf0100 +800002ec: f2410113 addi sp,sp,-220 # f00fff24 +800002f0: 01c12023 sw t3,0(sp) + +800002f4 : +800002f4: f0100137 lui sp,0xf0100 +800002f8: f2010113 addi sp,sp,-224 # f00fff20 +800002fc: 00012023 sw zero,0(sp) +80000300: 00000013 nop +80000304: 00000013 nop +80000308: 00000013 nop +8000030c: 00000013 nop +80000310: 00000013 nop +80000314: 00000013 nop diff --git a/src/test/cpp/raw/lrsc/build/lrsc.hex b/src/test/cpp/raw/lrsc/build/lrsc.hex new file mode 100644 index 0000000..7b96205 --- /dev/null +++ b/src/test/cpp/raw/lrsc/build/lrsc.hex @@ -0,0 +1,53 @@ +:0200000480007A +:100000006F00C00413000000130000001300000084 +:100010001300000013000000130000001300000094 +:10002000F32E003093FE0E08638A0E00B72E0000F8 +:10003000938E0E8073900E3073002030F32E1034A8 +:10004000938E4E0073901E3473002030130E1000F8 +:100050003705001093054006130650069306600608 +:100060002320D5002F26B51813071000631EE6269F +:1000700003270500639AE626130E200037050010BB +:100080001305450093057006130680069306900637 +:100090002320D5002F26B518130710006316E62479 +:1000A000032705006392E624130E30003705001085 +:1000B0001305450093057006130680069306900607 +:1000C0002F26B518130710006310E622032705003A +:1000D000639CE620130E40003705001013058500D1 +:1000E0009305A0061306B0069306C0062320D5008C +:1000F000AF2705102F26B5186398D71E6316061E66 +:10010000032705006392E51E130E5000370500100B +:10011000130585009305D0061306E0069306F00646 +:100120002320D5002F26B5186310061C03270500D1 +:10013000639CE51A130E6000370500101305C50017 +:1001400093050007130610079306200737040010D5 +:10015000130404019304300713094007930950075F +:100160002320D50023203401AF270510AF2A041027 +:100170002F26B5182F2994186398D71663160616DC +:10018000032705006392E51663903A17631E09146E +:10019000032A0400639A4415130E700037050010FB +:1001A0001305450193058007130690079306A007E2 +:1001B000930E00012320D500AF2705102F26B51878 +:1001C0006394D7126312061203270500639EE5109D +:1001D000938EFEFF13054500938535001306360008 +:1001E00093863600E3980EFC130E9000370500103E +:1001F000130505109305B0071306C0079306D00733 +:100200002320D500AF270510730000002F26B51856 +:1002100013071000631AE60C032705006396E60C2B +:10022000130EB000370500101305053093052008A4 +:1002300013063008930640082320D500B71E00009F +:10024000938E0E8073904E30930E8000AF27051072 +:1002500073900E3013000000130000001300000024 +:100260001300000013000000130000002F26B51833 +:1002700013071000631AE606032705006396E606D7 +:10028000130EC00037050010130505409305C00884 +:100290001306D0089306E0082320D500B71E0000FF +:1002A000938E0E8073904E30B72E0000938E8E800A +:1002B000AF27051073900E301300000013000000EC +:1002C00013000000130000001300000013000000E2 +:1002D0002F26B518130710006318E6000327050042 +:1002E0006394E6006F000001370110F0130141F242 +:1002F0002320C101370110F0130101F22320010076 +:1003000013000000130000001300000013000000A1 +:080310001300000013000000BF +:040000058000004C2B +:00000001FF diff --git a/src/test/cpp/raw/lrsc/makefile b/src/test/cpp/raw/lrsc/makefile new file mode 100644 index 0000000..eafdb26 --- /dev/null +++ b/src/test/cpp/raw/lrsc/makefile @@ -0,0 +1,5 @@ +PROJ_NAME=lrsc + +ATOMIC=yes + +include ../common/asm.mk \ No newline at end of file diff --git a/src/test/cpp/raw/lrsc/src/crt.S b/src/test/cpp/raw/lrsc/src/crt.S new file mode 100644 index 0000000..7fef5e3 --- /dev/null +++ b/src/test/cpp/raw/lrsc/src/crt.S @@ -0,0 +1,265 @@ +.globl _start + + + j _start + nop + nop + nop + nop + nop + nop + nop + +.global trap_entry +trap_entry: + csrr x29, mstatus + and x29, x29, 0x080 + beqz x29, notExternalInterrupt + li x29, 0x1800 //000 disable interrupts + csrw mstatus,x29 + mret + +notExternalInterrupt: + csrr x29, mepc + addi x29, x29, 4 + csrw mepc, x29 + mret + +_start: +//Test 1 SC on unreserved area should fail and not write memory + li x28, 1 + li a0, 0x10000000 + li a1, 100 + li a2, 101 + li a3, 102 + sw a3, 0(a0) + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a3, a4, fail + +//Test 2 SC on another unreserved area should fail and not write memory + li x28, 2 + li a0, 0x10000004 + li a1, 103 + li a2, 104 + li a3, 105 + sw a3, 0(a0) + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a3, a4, fail + + +//Test 3 retrying SC on unreserved area should fail and not write memory + li x28, 3 + li a0, 0x10000004 + li a1, 103 + li a2, 104 + li a3, 105 + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a3, a4, fail + + +//Test 4 SC on reserved area should pass and should be written write memory + li x28, 4 + li a0, 0x10000008 + li a1, 106 + li a2, 107 + li a3, 108 + sw a3, 0(a0) + lr.w a5, (a0) + sc.w a2, a1, (a0) + bne a5, a3, fail + bne a2, x0, fail + lw a4, 0(a0) + bne a1, a4, fail + + +//Test 5 redo SC on reserved area should pass and should be written write memory + li x28, 5 + li a0, 0x10000008 + li a1, 109 + li a2, 110 + li a3, 111 + sw a3, 0(a0) + sc.w a2, a1, (a0) + bne a2, x0, fail + lw a4, 0(a0) + bne a1, a4, fail + +//Test 6 Allow two entries at the same time + li x28, 6 + li a0, 0x1000000C + li a1, 112 + li a2, 113 + li a3, 114 + li s0, 0x10000010 + li s1, 115 + li s2, 116 + li s3, 117 + + sw a3, 0(a0) + sw s3, 0(s0) + lr.w a5, (a0) + lr.w s5, (s0) + sc.w a2, a1, (a0) + sc.w s2, s1, (s0) + bne a5, a3, fail + bne a2, x0, fail + lw a4, 0(a0) + bne a1, a4, fail + + bne s5, s3, fail + bne s2, x0, fail + lw s4, 0(s0) + bne s1, s4, fail + +//Test 7 do a lot of allocation to clear the entries + li x28, 7 + li a0, 0x10000014 + li a1, 120 + li a2, 121 + li a3, 122 + li x29, 16 +test7: + sw a3, 0(a0) + lr.w a5, (a0) + sc.w a2, a1, (a0) + bne a5, a3, fail + bne a2, x0, fail + lw a4, 0(a0) + bne a1, a4, fail + add x29, x29, -1 + add a0, a0, 4 + add a1, a1, 3 + add a2, a2, 3 + add a3, a3, 3 + bnez x29, test7 + + +//Test 8 SC on discarded entries should fail + /* li x28, 8 + li a0, 0x10000018 + li a1, 120 + li a2, 121 + li a3, 122 + lw a5, 0(a0) + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a5, a4, fail*/ + + +//Test 9 SC should fail after a context switching + li x28, 9 + li a0, 0x10000100 + li a1, 123 + li a2, 124 + li a3, 125 + sw a3, 0(a0) + lr.w a5, (a0) + scall + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a3, a4, fail + + + +//Test 10 SC should fail if the address doesn't match + /* li x28, 10 + li a0, 0x10000200 + li a6, 0x10000204 + li a1, 126 + li a2, 127 + li a3, 128 + li a7, 129 + sw a3, 0(a0) + sw a7, 0(a6) + lr.w a5, (a6) + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a6) + bne a7, a4, fail*/ + + + +//Test 11 SC should fail after a external interrupt context switching + li x28, 11 + li a0, 0x10000300 + li a1, 130 + li a2, 131 + li a3, 132 + sw a3, 0(a0) + li x29, 0x800 //800 external interrupts + csrw mie,x29 + li x29, 0x008 //008 enable interrupts + lr.w a5, (a0) + csrw mstatus,x29 //Enable external interrupt (will jump instantly due to testbench setup) + nop + nop + nop + nop + nop + nop + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a3, a4, fail + + +//Test 12 SC should fail after a external interrupt context switching (callback on lr) + li x28, 12 + li a0, 0x10000400 + li a1, 140 + li a2, 141 + li a3, 142 + sw a3, 0(a0) + li x29, 0x800 //800 external interrupts + csrw mie,x29 + li x29, 0x1808 //008 enable interrupts + lr.w a5, (a0) + csrw mstatus,x29 //Enable external interrupt (will jump instantly due to testbench setup) + nop + nop + nop + nop + nop + nop + sc.w a2, a1, (a0) + li a4, 1 + bne a2, a4, fail + lw a4, 0(a0) + bne a3, a4, fail + + + + j pass + + +fail: //x28 => error code + li x2, 0xF00FFF24 + sw x28, 0(x2) + +pass: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + + + nop + nop + nop + nop + nop + nop diff --git a/src/test/cpp/raw/lrsc/src/ld b/src/test/cpp/raw/lrsc/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/src/test/cpp/raw/lrsc/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index a6f43bf..8e1c146 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -3641,8 +3641,12 @@ int main(int argc, char **argv, char **env) { #endif - #ifdef ATOMIC - redo(REDO,WorkspaceRegression("atomic").loadHex("../custom/atomic/build/atomic.hex")->bootAt(0x00000000u)->run(10e3);); + #ifdef LRSC + redo(REDO,WorkspaceRegression("lrsc").loadHex("../raw/lrsc/build/lrsc.hex")->bootAt(0x00000000u)->run(10e3);); + #endif + + #ifdef AMO + redo(REDO,WorkspaceRegression("amo").loadHex("../raw/amo/build/amo.hex")->bootAt(0x00000000u)->run(10e3);); #endif #ifdef DHRYSTONE diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile index b178fee..1ffc036 100644 --- a/src/test/cpp/regression/makefile +++ b/src/test/cpp/regression/makefile @@ -14,7 +14,7 @@ EBREAK?=no FENCEI?=no MMU?=yes SEED?=no -ATOMIC?=no +LRSC?=no AMO?=no NO_STALL?=no DEBUG_PLUGIN?=STD @@ -143,8 +143,8 @@ ifeq ($(CSR),yes) endif -ifeq ($(ATOMIC),yes) - ADDCFLAGS += -CFLAGS -DATOMIC +ifeq ($(LRSC),yes) + ADDCFLAGS += -CFLAGS -DLRSC endif ifeq ($(AMO),yes)