diff --git a/README.md b/README.md
index 5d9d9f2..6b240a5 100644
--- a/README.md
+++ b/README.md
@@ -315,13 +315,13 @@ You can find multiples software examples and demo there : https://github.com/Spi
 There is some measurements of Murax SoC timings and area  :
 
 ```
-Murax interlocked stages (0.37 DMIPS/Mhz) ->
+Murax interlocked stages (0.45 DMIPS/Mhz) ->
   Artix 7    -> 304 Mhz 1016 LUT 1296 FF
   Cyclone V  -> 165 Mhz 736 ALMs
   Cyclone IV -> 151 Mhz 1,463 LUT 1,254 FF
   ICE40-HX   ->  51 Mhz 2387 LC (icestorm)
 
-MuraxFast bypassed stages (0.55 DMIPS/Mhz) ->
+MuraxFast bypassed stages (0.65 DMIPS/Mhz) ->
   Artix 7    -> 301 Mhz 1248 LUT 1393 FF
   Cyclone V  -> 163 Mhz 872 ALMs
   Cyclone IV -> 145 Mhz 1,712 LUT 1,288 FF
@@ -341,9 +341,40 @@ sbt "test:runMain vexriscv.MuraxSim"
 
 ## Build the RISC-V GCC
 
-In fact, now you can find some prebuild GCC : <br>
+To compile the Riscv GCC :
+
+```sh
+# Be carefull, sometime the git clone has issue to successfully clone riscv-gnu-toolchain.
+sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev -y
+
+git clone https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain
+cd riscv-gnu-toolchain
+git checkout bf5697a
+git submodule update --init --recursive
+
+sudo mkdir /opt/riscv32im
+sudo chown $USER /opt/riscv32im
+
+mkdir build; cd build
+../configure --with-arch=rv32im --prefix=/opt/riscv32im
+make -j$(nproc)
+cd ..
+
+sudo mkdir /opt/riscv32i
+sudo chown $USER /opt/riscv32i
+
+rm -rf build
+mkdir build; cd build
+../configure --with-arch=rv32i --prefix=/opt/riscv32i
+make -j$(nproc)
+```
+
+
+Else you can use a prebuild GCC : <br>
 - https://www.sifive.com/products/tools/   =>   SiFive GNU Embedded Toolchain
-The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/riscv/__contentOfThisPreBuild__
+The VexRiscvSocSoftware makefiles are expecting to find this prebuild version in /opt/riscv/__contentOfThisPreBuild__ . You will also have to set the SIFIVE_GCC_PACK environnement variable to yes to make it working with the VexRiscvSocSoftware.
+
+Note : It look like that this prebuild pack has performances issues with the dhrystone benchmark, so i don't realy recommand to use it.
 
 ```sh
 wget https://static.dev.sifive.com/dev-tools/riscv64-unknown-elf-gcc-20170612-x86_64-linux-centos6.tar.gz
@@ -353,35 +384,6 @@ sudo mv /opt/riscv64-unknown-elf-gcc-20170612-x86_64-linux-centos6 /opt/riscv
 echo 'export PATH=/opt/riscv/bin:$PATH' >> ~/.bashrc 
 ```
 
-But if you want to compile from sources in /opt/ the rv32i and rv32im gcc, do the following (will take one hour):
-
-```sh
-# Be carefull, sometime the git clone has issue to successfully clone riscv-gnu-toolchain.
-sudo apt-get install autoconf automake autotools-dev curl libmpc-dev libmpfr-dev libgmp-dev gawk build-essential bison flex texinfo gperf libtool patchutils bc zlib1g-dev -y
-
-git clone --recursive https://github.com/riscv/riscv-gnu-toolchain riscv-gnu-toolchain
-cd riscv-gnu-toolchain
-
-echo "Starting RISC-V Toolchain build process"
-
-ARCH=rv32im
-rmdir -rf $ARCH
-mkdir $ARCH; cd $ARCH
-../configure  --prefix=/opt/$ARCH --with-arch=$ARCH --with-abi=ilp32
-sudo make -j4
-cd ..
-
-
-ARCH=rv32i
-rmdir -rf $ARCH
-mkdir $ARCH; cd $ARCH
-../configure  --prefix=/opt/$ARCH --with-arch=$ARCH --with-abi=ilp32
-sudo make -j4
-cd ..
-
-echo -e "\\nRISC-V Toolchain installation completed!"
-```
-
 ## CPU parametrization and instantiation example
 
 You can find many example of different config in the https://github.com/SpinalHDL/VexRiscv/tree/master/src/main/scala/vexriscv/demo folder. There is one :