From 7a9f7c4fb9f9602c2ea370785d9bea0488bb7e3b Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Tue, 26 Mar 2019 16:30:53 +0100 Subject: [PATCH 1/8] Untested cacheless buses to AHB bridges --- .../vexriscv/plugin/DBusSimplePlugin.scala | 28 +++++++++++ .../vexriscv/plugin/IBusSimplePlugin.scala | 26 ++++++++++ src/test/cpp/regression/main.cpp | 49 +++++++++++++++++++ 3 files changed, 103 insertions(+) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index eb4ce46..9ef1121 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -3,6 +3,7 @@ package vexriscv.plugin import vexriscv._ import spinal.core._ import spinal.lib._ +import spinal.lib.bus.amba3.ahblite.{AhbLite3Config, AhbLite3Master} import spinal.lib.bus.amba4.axi._ import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig} import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig} @@ -63,6 +64,11 @@ object DBusSimpleBus{ useBTE = true, useCTI = true ) + + def getAhbLite3Config() = AhbLite3Config( + addressWidth = 32, + dataWidth = 32 + ) } case class DBusSimpleBus() extends Bundle with IMasterSlave{ @@ -195,6 +201,28 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ bus } + + + + def toAhbLite3Master(): AhbLite3Master = { + val bus = AhbLite3Master(DBusSimpleBus.getAhbLite3Config()) + bus.HADDR := this.cmd.address + bus.HWRITE := this.cmd.wr + bus.HSIZE := B(this.cmd.size, 3 bits) + bus.HBURST := 0 + bus.HPROT := "1111" + bus.HTRANS := B"0" ## this.cmd.valid + bus.HMASTLOCK := False + bus.HWDATA := RegNextWhen(this.cmd.data, bus.HREADY) + this.cmd.ready := bus.HREADY + + val pending = RegInit(False) clearWhen(bus.HREADY) setWhen(this.cmd.fire && !this.cmd.wr) + this.rsp.ready := bus.HREADY + this.rsp.data := bus.HRDATA + this.rsp.error := bus.HRESP + bus + } + } diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 636b193..a3f6a5b 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -3,6 +3,7 @@ package vexriscv.plugin import vexriscv._ import spinal.core._ import spinal.lib._ +import spinal.lib.bus.amba3.ahblite.{AhbLite3, AhbLite3Config, AhbLite3Master} import spinal.lib.bus.amba4.axi._ import spinal.lib.bus.avalon.{AvalonMM, AvalonMMConfig} import spinal.lib.bus.wishbone.{Wishbone, WishboneConfig} @@ -59,6 +60,11 @@ object IBusSimpleBus{ useBTE = true, useCTI = true ) + + def getAhbLite3Config() = AhbLite3Config( + addressWidth = 32, + dataWidth = 32 + ) } @@ -147,6 +153,26 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit rsp.error := False bus } + + //cmdForkPersistence need to bet set + def toAhbLite3Master(): AhbLite3Master = { + val bus = AhbLite3Master(IBusSimpleBus.getAhbLite3Config()) + bus.HADDR := this.cmd.pc + bus.HWRITE := False + bus.HSIZE := 2 + bus.HBURST := 0 + bus.HPROT := "1110" + bus.HTRANS := B"0" ## this.cmd.valid + bus.HMASTLOCK := False + bus.HWDATA.assignDontCare() + this.cmd.ready := bus.HREADY + + val pending = RegInit(False) clearWhen(bus.HREADY) setWhen(this.cmd.fire) + this.rsp.valid := pending && bus.HREADY + this.rsp.inst := bus.HRDATA + this.rsp.error := bus.HRESP + bus + } } diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index a5c1b0d..1c74161 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -1279,6 +1279,50 @@ public: #endif + +#ifdef IBUS_SIMPLE_AHBLITE3 +class IBusSimpleAhbLite3 : public SimElement{ +public: + Workspace *ws; + VVexRiscv* top; + + uint32_t iBusAhbLite3_HRDATA; + bool iBusAhbLite3_HRESP, iBusAhbLite3_HREADY; + + IBusSimpleAhbLite3(Workspace* ws){ + this->ws = ws; + this->top = ws->top; + } + + virtual void onReset(){ + top->iBusAhbLite3_HREADY = 1; + top->iBusAhbLite3_HRESP = 0; + } + + virtual void preCycle(){ + if (top->iBusAhbLite3_HTRANS == 2 && top->iBusAhbLite3_HREADY && !top->iBusAhbLite3_HWRITE) { + ws->iBusAccess(top->iBusAhbLite3_HADDR,&iBusAhbLite3_HRDATA,&iBusAhbLite3_HRESP); + } + } + + virtual void postCycle(){ + if(top->iBusAhbLite3_HREADY && (!ws->iStall || VL_RANDOM_I(7) < 100)){ + IBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop(); + top->iBusAhbLite3_HRDATA = iBusAhbLite3_HRDATA; + top->iBusAhbLite3_HREADY = iBusAhbLite3_HREADY; + top->iBusAhbLite3_HRESP = iBusAhbLite3_HRESP; + } else { + top->iBusAhbLite3_HRESP = 0; + top->iBusAhbLite3_HRDATA = VL_RANDOM_I(32); + top->iBusAhbLite3_HRESP = VL_RANDOM_I(1); + } + if(ws->iStall) + top->iBusAhbLite3_HREADY = VL_RANDOM_I(7) < 100; + } +}; +#endif + + #ifdef IBUS_CACHED class IBusCached : public SimElement{ public: @@ -1994,6 +2038,11 @@ void Workspace::fillSimELements(){ #ifdef IBUS_SIMPLE_AVALON simElements.push_back(new IBusSimpleAvalon(this)); #endif + #ifdef IBUS_SIMPLE_AHBLITE3 + simElements.push_back(new IBusSimpleAhbLite3(this)); + #endif + + #ifdef IBUS_CACHED simElements.push_back(new IBusCached(this)); #endif From b0522cb4918c4fe3b91dc7d9325f79e060fd59ea Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 28 Mar 2019 08:32:12 +0100 Subject: [PATCH 2/8] Add AhbLite3 simulation config --- .../demo/VexRiscvAhbLite3ForSim.scala | 177 ++++++++++++++++++ 1 file changed, 177 insertions(+) create mode 100644 src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala diff --git a/src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala new file mode 100644 index 0000000..2a2613f --- /dev/null +++ b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala @@ -0,0 +1,177 @@ +package vexriscv.demo + +import spinal.core._ +import spinal.lib._ +import spinal.lib.bus.avalon.AvalonMM +import spinal.lib.eda.altera.{InterruptReceiverTag, QSysify, ResetEmitterTag} +import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} +import vexriscv.plugin._ +import vexriscv.{VexRiscv, VexRiscvConfig, plugin} + +/** + * Created by spinalvm on 14.07.17. + */ +//class VexRiscvAvalon(debugClockDomain : ClockDomain) extends Component{ +// +//} + +//make clean run DBUS=CACHED_AVALON IBUS=CACHED_AVALON MMU=no CSR=no DEBUG_PLUGIN=AVALON + +object VexRiscvAhbLite3ForSim{ + def main(args: Array[String]) { + val report = SpinalVerilog{ + + //CPU configuration + val cpuConfig = VexRiscvConfig( + plugins = List( + new IBusSimplePlugin( + resetVector = 0x80000000l, + cmdForkOnSecondStage = false, + cmdForkPersistence = true, + prediction = STATIC, + catchAccessFault = false, + compressedGen = false + ), + new DBusSimplePlugin( + catchAddressMisaligned = false, + catchAccessFault = false + ), +// new IBusCachedPlugin( +// config = InstructionCacheConfig( +// cacheSize = 4096, +// bytePerLine =32, +// wayCount = 1, +// addressWidth = 32, +// cpuDataWidth = 32, +// memDataWidth = 32, +// catchIllegalAccess = true, +// catchAccessFault = true, +// catchMemoryTranslationMiss = true, +// asyncTagMemory = false, +// twoCycleRam = true +// ) +// // askMemoryTranslation = true, +// // memoryTranslatorPortConfig = MemoryTranslatorPortConfig( +// // portTlbSize = 4 +// // ) +// ), +// new DBusCachedPlugin( +// config = new DataCacheConfig( +// cacheSize = 4096, +// bytePerLine = 32, +// wayCount = 1, +// addressWidth = 32, +// cpuDataWidth = 32, +// memDataWidth = 32, +// catchAccessError = true, +// catchIllegal = true, +// catchUnaligned = true, +// catchMemoryTranslationMiss = true +// ), +// memoryTranslatorPortConfig = null +// // memoryTranslatorPortConfig = MemoryTranslatorPortConfig( +// // portTlbSize = 6 +// // ) +// ), + new StaticMemoryTranslatorPlugin( + ioRange = _(31 downto 28) === 0xF + ), + new DecoderSimplePlugin( + catchIllegalInstruction = true + ), + new RegFilePlugin( + regFileReadyKind = plugin.SYNC, + zeroBoot = false + ), + new IntAluPlugin, + new SrcPlugin( + separatedAddSub = false, + executeInsertion = true + ), + new FullBarrelShifterPlugin, + new MulPlugin, + new DivPlugin, + new HazardSimplePlugin( + bypassExecute = true, + bypassMemory = true, + bypassWriteBack = true, + bypassWriteBackBuffer = true, + pessimisticUseSrc = false, + pessimisticWriteRegFile = false, + pessimisticAddressMatch = false + ), + new DebugPlugin(ClockDomain.current.clone(reset = Bool().setName("debugReset"))), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = true + ), + new CsrPlugin( + config = CsrPluginConfig( + catchIllegalAccess = false, + mvendorid = null, + marchid = null, + mimpid = null, + mhartid = null, + misaExtensionsInit = 66, + misaAccess = CsrAccess.NONE, + mtvecAccess = CsrAccess.NONE, + mtvecInit = 0x00000020l, + mepcAccess = CsrAccess.READ_WRITE, + mscratchGen = false, + mcauseAccess = CsrAccess.READ_ONLY, + mbadaddrAccess = CsrAccess.READ_ONLY, + mcycleAccess = CsrAccess.NONE, + minstretAccess = CsrAccess.NONE, + ecallGen = false, + wfiGenAsWait = false, + ucycleAccess = CsrAccess.NONE + ) + ), + new YamlPlugin("cpu0.yaml") + ) + ) + + //CPU instanciation + val cpu = new VexRiscv(cpuConfig) + + //CPU modifications to be an AhbLite3 one + cpu.rework { + for (plugin <- cpuConfig.plugins) plugin match { + case plugin: IBusSimplePlugin => { + plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus + master(plugin.iBus.toAhbLite3Master()).setName("iBusAhbLite3") + } +// case plugin: DBusSimplePlugin => { +// plugin.dBus.setAsDirectionLess() +// master(plugin.dBus.toAhbLite3Master()).setName("dBusAhbLite3") +// } +// case plugin: IBusCachedPlugin => { +// plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus +// iBus = master(plugin.iBus.toAvalon()) +// .setName("iBusAvalon") +// .addTag(ClockDomainTag(ClockDomain.current)) //Specify a clock domain to the iBus (used by QSysify) +// } +// case plugin: DBusCachedPlugin => { +// plugin.dBus.setAsDirectionLess() +// master(plugin.dBus.toAvalon()) +// .setName("dBusAvalon") +// .addTag(ClockDomainTag(ClockDomain.current)) +// } +// case plugin: DebugPlugin => plugin.debugClockDomain { +// plugin.io.bus.setAsDirectionLess() +// slave(plugin.io.bus.fromAvalon()) +// .setName("debugBusAvalon") +// .addTag(ClockDomainTag(plugin.debugClockDomain)) +// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit +// plugin.io.resetOut +// .addTag(ResetEmitterTag(plugin.debugClockDomain)) +// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit +// } + case _ => + } + } + cpu + } + } +} + From 53c05c31c7a7f185b9f4af642dcecaa2cfa9e167 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 28 Mar 2019 10:12:42 +0100 Subject: [PATCH 3/8] IBusSimplePlugin AHB bridge fix, pass tests --- .../vexriscv/plugin/DBusSimplePlugin.scala | 2 +- .../vexriscv/plugin/IBusSimplePlugin.scala | 2 +- src/test/cpp/regression/main.cpp | 18 ++++++++++-------- 3 files changed, 12 insertions(+), 10 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 9ef1121..fcafd3a 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -211,7 +211,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ bus.HSIZE := B(this.cmd.size, 3 bits) bus.HBURST := 0 bus.HPROT := "1111" - bus.HTRANS := B"0" ## this.cmd.valid + bus.HTRANS := this.cmd.valid ## B"0" bus.HMASTLOCK := False bus.HWDATA := RegNextWhen(this.cmd.data, bus.HREADY) this.cmd.ready := bus.HREADY diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index a3f6a5b..8f23337 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -162,7 +162,7 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit bus.HSIZE := 2 bus.HBURST := 0 bus.HPROT := "1110" - bus.HTRANS := B"0" ## this.cmd.valid + bus.HTRANS := this.cmd.valid ## B"0" bus.HMASTLOCK := False bus.HWDATA.assignDontCare() this.cmd.ready := bus.HREADY diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 1c74161..8ac4ffe 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -972,7 +972,7 @@ public: if(bootPc != -1) top->VexRiscv->core->prefetch_pc = bootPc; #else if(bootPc != -1) { - #if defined(IBUS_SIMPLE) || defined(IBUS_SIMPLE_WISHBONE) + #if defined(IBUS_SIMPLE) || defined(IBUS_SIMPLE_WISHBONE) || defined(IBUS_SIMPLE_AHBLITE3) top->VexRiscv->IBusSimplePlugin_fetchPc_pcReg = bootPc; #ifdef COMPRESSED top->VexRiscv->IBusSimplePlugin_decodePc_pcReg = bootPc; @@ -1287,7 +1287,8 @@ public: VVexRiscv* top; uint32_t iBusAhbLite3_HRDATA; - bool iBusAhbLite3_HRESP, iBusAhbLite3_HREADY; + bool iBusAhbLite3_HRESP; + bool pending; IBusSimpleAhbLite3(Workspace* ws){ this->ws = ws; @@ -1295,6 +1296,7 @@ public: } virtual void onReset(){ + pending = false; top->iBusAhbLite3_HREADY = 1; top->iBusAhbLite3_HRESP = 0; } @@ -1302,22 +1304,22 @@ public: virtual void preCycle(){ if (top->iBusAhbLite3_HTRANS == 2 && top->iBusAhbLite3_HREADY && !top->iBusAhbLite3_HWRITE) { ws->iBusAccess(top->iBusAhbLite3_HADDR,&iBusAhbLite3_HRDATA,&iBusAhbLite3_HRESP); + pending = true; } } virtual void postCycle(){ - if(top->iBusAhbLite3_HREADY && (!ws->iStall || VL_RANDOM_I(7) < 100)){ - IBusSimpleAvalonRsp rsp = rsps.front(); rsps.pop(); + if(ws->iStall) + top->iBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I(7) < 100); + + if(pending && top->iBusAhbLite3_HREADY){ top->iBusAhbLite3_HRDATA = iBusAhbLite3_HRDATA; - top->iBusAhbLite3_HREADY = iBusAhbLite3_HREADY; top->iBusAhbLite3_HRESP = iBusAhbLite3_HRESP; + pending = false; } else { - top->iBusAhbLite3_HRESP = 0; top->iBusAhbLite3_HRDATA = VL_RANDOM_I(32); top->iBusAhbLite3_HRESP = VL_RANDOM_I(1); } - if(ws->iStall) - top->iBusAhbLite3_HREADY = VL_RANDOM_I(7) < 100; } }; #endif From ad27007c3cb53ede7db2f37928312a412d652871 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Thu, 28 Mar 2019 11:41:49 +0100 Subject: [PATCH 4/8] DBusSimplePlugin AHB bridge add hazard checking, pass tests --- .../demo/VexRiscvAhbLite3ForSim.scala | 8 +-- .../vexriscv/plugin/DBusSimplePlugin.scala | 12 +++- src/test/cpp/regression/main.cpp | 57 +++++++++++++++++++ 3 files changed, 72 insertions(+), 5 deletions(-) diff --git a/src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala index 2a2613f..d11994b 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala @@ -141,10 +141,10 @@ object VexRiscvAhbLite3ForSim{ plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus master(plugin.iBus.toAhbLite3Master()).setName("iBusAhbLite3") } -// case plugin: DBusSimplePlugin => { -// plugin.dBus.setAsDirectionLess() -// master(plugin.dBus.toAhbLite3Master()).setName("dBusAhbLite3") -// } + case plugin: DBusSimplePlugin => { + plugin.dBus.setAsDirectionLess() + master(plugin.dBus.toAhbLite3Master(avoidWriteToReadHazard = true)).setName("dBusAhbLite3") + } // case plugin: IBusCachedPlugin => { // plugin.iBus.setAsDirectionLess() //Unset IO properties of iBus // iBus = master(plugin.iBus.toAvalon()) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index fcafd3a..266c762 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -204,7 +204,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ - def toAhbLite3Master(): AhbLite3Master = { + def toAhbLite3Master(avoidWriteToReadHazard : Boolean): AhbLite3Master = { val bus = AhbLite3Master(DBusSimpleBus.getAhbLite3Config()) bus.HADDR := this.cmd.address bus.HWRITE := this.cmd.wr @@ -220,6 +220,16 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ this.rsp.ready := bus.HREADY this.rsp.data := bus.HRDATA this.rsp.error := bus.HRESP + + if(avoidWriteToReadHazard) { + val writeDataPhase = RegNextWhen(bus.HTRANS === 2 && bus.HWRITE, bus.HREADY) init (False) + val potentialHazard = this.cmd.valid && !this.cmd.wr && writeDataPhase + when(potentialHazard) { + bus.HTRANS := 0 + this.cmd.ready := False + } + } + bus } diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 8ac4ffe..f81183d 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -1572,6 +1572,60 @@ public: }; #endif + + +#ifdef DBUS_SIMPLE_AHBLITE3 +class DBusSimpleAhbLite3 : public SimElement{ +public: + Workspace *ws; + VVexRiscv* top; + + uint32_t dBusAhbLite3_HADDR, dBusAhbLite3_HSIZE, dBusAhbLite3_HTRANS, dBusAhbLite3_HWRITE; + + DBusSimpleAhbLite3(Workspace* ws){ + this->ws = ws; + this->top = ws->top; + } + + virtual void onReset(){ + top->dBusAhbLite3_HREADY = 1; + top->dBusAhbLite3_HRESP = 0; + dBusAhbLite3_HTRANS = 0; + } + + virtual void preCycle(){ + if(top->dBusAhbLite3_HREADY && dBusAhbLite3_HTRANS == 2 && dBusAhbLite3_HWRITE){ + uint32_t data = top->dBusAhbLite3_HWDATA; + bool error; + ws->dBusAccess(dBusAhbLite3_HADDR, 1, dBusAhbLite3_HSIZE, ((1 << (1 << dBusAhbLite3_HSIZE))-1) << (dBusAhbLite3_HADDR & 0x3),&data,&error); + } + + if(top->dBusAhbLite3_HREADY){ + dBusAhbLite3_HADDR = top->dBusAhbLite3_HADDR ; + dBusAhbLite3_HSIZE = top->dBusAhbLite3_HSIZE ; + dBusAhbLite3_HTRANS = top->dBusAhbLite3_HTRANS ; + dBusAhbLite3_HWRITE = top->dBusAhbLite3_HWRITE ; + } + } + + virtual void postCycle(){ + if(ws->iStall) + top->dBusAhbLite3_HREADY = (!ws->iStall || VL_RANDOM_I(7) < 100); + + top->dBusAhbLite3_HRDATA = VL_RANDOM_I(32); + top->dBusAhbLite3_HRESP = VL_RANDOM_I(1); + + if(top->dBusAhbLite3_HREADY && dBusAhbLite3_HTRANS == 2 && !dBusAhbLite3_HWRITE){ + + bool error; + ws->dBusAccess(dBusAhbLite3_HADDR, 0, dBusAhbLite3_HSIZE, ((1 << (1 << dBusAhbLite3_HSIZE))-1) << (dBusAhbLite3_HADDR & 0x3),&top->dBusAhbLite3_HRDATA,&error); + top->dBusAhbLite3_HRESP = error; + } + } +}; +#endif + + #if defined(DBUS_CACHED_WISHBONE) || defined(DBUS_SIMPLE_WISHBONE) #include @@ -2065,6 +2119,9 @@ void Workspace::fillSimELements(){ #ifdef DBUS_SIMPLE_AVALON simElements.push_back(new DBusSimpleAvalon(this)); #endif + #ifdef DBUS_SIMPLE_AHBLITE3 + simElements.push_back(new DBusSimpleAhbLite3(this)); + #endif #ifdef DBUS_CACHED simElements.push_back(new DBusCached(this)); #endif From d2b324e32bf88713e27257c191976e772db3cd48 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 15 Apr 2019 11:01:51 +0200 Subject: [PATCH 5/8] Add jtag and vhdl option --- ...te3ForSim.scala => VexRiscvAhbLite3.scala} | 23 ++++++++----------- 1 file changed, 10 insertions(+), 13 deletions(-) rename src/main/scala/vexriscv/demo/{VexRiscvAhbLite3ForSim.scala => VexRiscvAhbLite3.scala} (88%) diff --git a/src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala similarity index 88% rename from src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala rename to src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala index d11994b..593d399 100644 --- a/src/main/scala/vexriscv/demo/VexRiscvAhbLite3ForSim.scala +++ b/src/main/scala/vexriscv/demo/VexRiscvAhbLite3.scala @@ -1,8 +1,10 @@ package vexriscv.demo + import spinal.core._ import spinal.lib._ import spinal.lib.bus.avalon.AvalonMM +import spinal.lib.com.jtag.Jtag import spinal.lib.eda.altera.{InterruptReceiverTag, QSysify, ResetEmitterTag} import vexriscv.ip.{DataCacheConfig, InstructionCacheConfig} import vexriscv.plugin._ @@ -15,11 +17,11 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin} // //} -//make clean run DBUS=CACHED_AVALON IBUS=CACHED_AVALON MMU=no CSR=no DEBUG_PLUGIN=AVALON +//make clean run DBUS=SIMPLE_AHBLITE3 IBUS=SIMPLE_AHBLITE3 MMU=no CSR=no DEBUG_PLUGIN=STD -object VexRiscvAhbLite3ForSim{ +object VexRiscvAhbLite3{ def main(args: Array[String]) { - val report = SpinalVerilog{ + val report = SpinalConfig(mode = if(args.contains("--vhdl")) VHDL else Verilog).generate{ //CPU configuration val cpuConfig = VexRiscvConfig( @@ -157,16 +159,11 @@ object VexRiscvAhbLite3ForSim{ // .setName("dBusAvalon") // .addTag(ClockDomainTag(ClockDomain.current)) // } -// case plugin: DebugPlugin => plugin.debugClockDomain { -// plugin.io.bus.setAsDirectionLess() -// slave(plugin.io.bus.fromAvalon()) -// .setName("debugBusAvalon") -// .addTag(ClockDomainTag(plugin.debugClockDomain)) -// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit -// plugin.io.resetOut -// .addTag(ResetEmitterTag(plugin.debugClockDomain)) -// .parent = null //Avoid the io bundle to be interpreted as a QSys conduit -// } + case plugin: DebugPlugin if args.contains("--jtag")=> plugin.debugClockDomain { + plugin.io.bus.setAsDirectionLess() + val jtag = slave(new Jtag()).setName("jtag") + jtag <> plugin.io.bus.fromJtag() + } case _ => } } From 7d99a70e9c3b95d6d2a9bfe481c4115e929ff119 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Wed, 1 May 2019 12:02:27 +0200 Subject: [PATCH 6/8] Switch to released SpinalHDL --- build.sbt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/build.sbt b/build.sbt index 29cebe0..f61c4ab 100644 --- a/build.sbt +++ b/build.sbt @@ -7,16 +7,16 @@ lazy val root = (project in file(".")). version := "2.0.0" )), libraryDependencies ++= Seq( - "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.3.3", - "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.3.3", +// "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.3.3", +// "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.3.3", "org.scalatest" % "scalatest_2.11" % "2.2.1", "org.yaml" % "snakeyaml" % "1.8" ), name := "VexRiscv" - )//.dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib) -//lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "sim") -//lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "core") -//lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "lib") + ).dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib) +lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "sim") +lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "core") +lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "lib") fork := true \ No newline at end of file From c7382466107697899daf80e55f7604fa2086e201 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Wed, 1 May 2019 12:03:01 +0200 Subject: [PATCH 7/8] Remove the legacy pipelining from Axi4 cacheless bridges --- .../scala/vexriscv/plugin/DBusSimplePlugin.scala | 15 +++------------ .../scala/vexriscv/plugin/IBusSimplePlugin.scala | 16 +++++----------- 2 files changed, 8 insertions(+), 23 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala index 8d23548..75b034d 100644 --- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala @@ -82,7 +82,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ slave(rsp) } - def toAxi4Shared(stageCmd : Boolean = true): Axi4Shared = { + def toAxi4Shared(stageCmd : Boolean = false): Axi4Shared = { val axi = Axi4Shared(DBusSimpleBus.getAxi4Config()) val pendingWritesMax = 7 val pendingWrites = CounterUpDown( @@ -92,7 +92,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ ) val cmdPreFork = if (stageCmd) cmd.stage.stage().s2mPipe() else cmd - val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen((pendingWrites =/= 0 && !cmdPreFork.wr) || pendingWrites === pendingWritesMax)) + val (cmdFork, dataFork) = StreamFork2(cmdPreFork.haltWhen((pendingWrites =/= 0 && cmdPreFork.valid && !cmdPreFork.wr) || pendingWrites === pendingWritesMax)) axi.sharedCmd.arbitrationFrom(cmdFork) axi.sharedCmd.write := cmdFork.wr axi.sharedCmd.prot := "010" @@ -117,16 +117,7 @@ case class DBusSimpleBus() extends Bundle with IMasterSlave{ axi.r.ready := True axi.b.ready := True - - - //TODO remove - val axi2 = Axi4Shared(DBusSimpleBus.getAxi4Config()) - axi.arw >-> axi2.arw - axi.w >> axi2.w - axi.r << axi2.r - axi.b << axi2.b -// axi2 << axi - axi2 + axi } def toAxi4(stageCmd : Boolean = true) = this.toAxi4Shared(stageCmd).toAxi4() diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala index 5b1d7ef..eef8d26 100644 --- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala +++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala @@ -68,7 +68,7 @@ object IBusSimpleBus{ } -case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle with IMasterSlave { +case class IBusSimpleBus(cmdIsPersistente : Boolean = false) extends Bundle with IMasterSlave { var cmd = Stream(IBusSimpleCmd()) var rsp = Flow(IBusSimpleRsp()) @@ -79,7 +79,7 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit def toAxi4ReadOnly(): Axi4ReadOnly = { - assert(!interfaceKeepData) + assert(cmdIsPersistente) val axi = Axi4ReadOnly(IBusSimpleBus.getAxi4Config()) axi.ar.valid := cmd.valid @@ -94,17 +94,11 @@ case class IBusSimpleBus(interfaceKeepData : Boolean = false) extends Bundle wit rsp.error := !axi.r.isOKAY() axi.r.ready := True - - //TODO remove - val axi2 = Axi4ReadOnly(IBusSimpleBus.getAxi4Config()) - axi.ar >-> axi2.ar - axi.r << axi2.r -// axi2 << axi - axi2 + axi } def toAvalon(): AvalonMM = { - assert(!interfaceKeepData) + assert(cmdIsPersistente) val avalonConfig = IBusSimpleBus.getAvalonConfig() val mm = AvalonMM(avalonConfig) @@ -199,7 +193,7 @@ class IBusSimplePlugin(resetVector : BigInt, override def setup(pipeline: VexRiscv): Unit = { super.setup(pipeline) - iBus = master(IBusSimpleBus(false)).setName("iBus") + iBus = master(IBusSimpleBus(cmdForkPersistence)).setName("iBus") val decoderService = pipeline.service(classOf[DecoderService]) decoderService.add(FENCE_I, Nil) From 8201cff7ff64395a9429ceb433dad1bb2b982440 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Fri, 10 May 2019 14:27:14 +0200 Subject: [PATCH 8/8] SpinalHDL 1.3.4 --- build.sbt | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/build.sbt b/build.sbt index f61c4ab..1db0792 100644 --- a/build.sbt +++ b/build.sbt @@ -7,16 +7,16 @@ lazy val root = (project in file(".")). version := "2.0.0" )), libraryDependencies ++= Seq( -// "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.3.3", -// "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.3.3", + "com.github.spinalhdl" % "spinalhdl-core_2.11" % "1.3.4", + "com.github.spinalhdl" % "spinalhdl-lib_2.11" % "1.3.4", "org.scalatest" % "scalatest_2.11" % "2.2.1", "org.yaml" % "snakeyaml" % "1.8" ), name := "VexRiscv" - ).dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib) -lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "sim") -lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "core") -lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "lib") + )//.dependsOn(spinalHdlSim,spinalHdlCore,spinalHdlLib) +//lazy val spinalHdlSim = ProjectRef(file("../SpinalHDL"), "sim") +//lazy val spinalHdlCore = ProjectRef(file("../SpinalHDL"), "core") +//lazy val spinalHdlLib = ProjectRef(file("../SpinalHDL"), "lib") fork := true \ No newline at end of file