From ac59eebb8d31a11aa0565129874d7edc3eaf5624 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Thu, 3 Aug 2017 21:58:23 +0200 Subject: [PATCH] Add Murax configuration which integrate a boot programme : Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin) --- src/main/ressource/hex/muraxDemo.hex | 76 +++++++++++++++ src/main/scala/vexriscv/TestsWorkspace.scala | 98 ++++++++++---------- src/main/scala/vexriscv/demo/Murax.scala | 44 +++++++++ 3 files changed, 169 insertions(+), 49 deletions(-) create mode 100644 src/main/ressource/hex/muraxDemo.hex diff --git a/src/main/ressource/hex/muraxDemo.hex b/src/main/ressource/hex/muraxDemo.hex new file mode 100644 index 0000000..ab31b8a --- /dev/null +++ b/src/main/ressource/hex/muraxDemo.hex @@ -0,0 +1,76 @@ +:100000006F00000B1300000013000000130000003D +:100010001300000013000000130000001300000094 +:10002000232E11FE232C51FE232A61FE232871FE6C +:100030002326A1FE2324B1FE2322C1FE2320D1FECC +:10004000232EE1FC232CF1FC232A01FD232811FDA2 +:100050002326C1FD2324D1FD2322E1FD2320F1FD30 +:10006000130101FCEF00403B8320C1038322810385 +:1000700003234103832301030325C1028325810256 +:1000800003264102832601020327C1018327810140 +:100090000328410183280101032EC100832E810022 +:1000A000032F4100832F010013010104730020304E +:1000B000170100001301017F130540011300000028 +:1000C00013000000130000001305F5FFE31805FE00 +:1000D000170500001305453C970500009385C53BB7 +:1000E0006308B50023200500130545006FF05FFF8E +:1000F000170500001305453A1301C1FF97050000DD +:1001000093858539630EB5008326050013054500E8 +:100110002320A100E7800600032501006FF01FFEE9 +:100120001301410037150000130505887310453091 +:100130001305800073100530EF00C0196F00000038 +:10014000130101FE232E8100130401022326A4FEC5 +:100150008327C4FE23A007008327C4FE23A407002F +:10016000130000000324C101130101026780000095 +:10017000130101FE232E8100130401022326A4FE95 +:10018000130000000324C101130101026780000075 +:10019000130101FE232E8100130401022326A4FE75 +:1001A0008327C4FE23A207008327C4FE1307F0FFA2 +:1001B00023A0E700130000000324C1011301010282 +:1001C00067800000130101FE232E81001304010249 +:1001D0002326A4FE8327C4FE83A7470093D70701E5 +:1001E00093F7F70F138507000324C10113010102E0 +:1001F00067800000130101FE232E81001304010219 +:100200002326A4FE8327C4FE83A7470093D7870134 +:10021000138507000324C101130101026780000058 +:10022000130101FE232E1100232C8100130401026F +:100230002326A4FE2324B4FE130000000325C4FEDD +:10024000EFF05FF893070500E38A07FE8327C4FEFB +:10025000032784FE23A0E700130000008320C101D0 +:10026000032481011301010267800000130101FED4 +:10027000232E8100130401022326A4FE2324B4FEAE +:10028000832784FE03A7C7008327C4FE23A4E700B7 +:10029000832784FE83A707001387F7FF832784FE45 +:1002A00083A74700939787003367F700832784FE6F +:1002B00083A78700939707013367F7008327C4FE5E +:1002C00023A6E700130000000324C101130101026B +:1002D00067800000130101FD2326110223248102FF +:1002E00013040103930710002322F4FE9307200058 +:1002F0002320F4FE93073000232EF4FC232604FE73 +:10030000B70702F013850701EFF09FE8370502F009 +:10031000EFF01FE6B70702F013850704EFF05FE286 +:10032000B70702F0373700001307F7ED23A0E70007 +:10033000B70702F0938707041307703E23A2E70074 +:10034000B70702F093870704370701001307270058 +:1003500023A0E700B70702F0938707011307F00017 +:1003600023A0E700B70702F09387070113071000E7 +:1003700023A2E700B70700F01307F00F23A4E7005C +:10038000B70700F023A20700B70701F0130720000A +:1003900023A2E700B70701F01307100423A0E7002A +:1003A000832744FE0327C4FEB307F7002326F4FE89 +:1003B000032704FE8327C4FDB307F7000327C4FE09 +:1003C000B307F7002326F4FE232404FE6F00000188 +:1003D000832784FE938717002324F4FE032784FEDB +:1003E000B7C700009387F734E3F4E7FEB70700F0E0 +:1003F00083A7470093F607FCB70700F083A74700E1 +:100400009387170013F7F703B70700F033E7E60009 +:1004100023A2E7006FF0DFF8130101FF232681001C +:1004200013040101B70702F09387070183A70700B0 +:1004300093F7170063800704B70700F003A747008E +:10044000B70700F01347070823A2E700B70702F039 +:10045000938707011307100023A0E7006F008001B6 +:10046000B70701F003A70700B70701F01377F70FED +:1004700023A0E700B70701F083A7470093F7072001 +:10048000E39007FE130000000324C10013010101E3 +:040490006780000081 +:04000003000000B049 +:00000001FF diff --git a/src/main/scala/vexriscv/TestsWorkspace.scala b/src/main/scala/vexriscv/TestsWorkspace.scala index 44a5150..99a379d 100644 --- a/src/main/scala/vexriscv/TestsWorkspace.scala +++ b/src/main/scala/vexriscv/TestsWorkspace.scala @@ -35,61 +35,61 @@ object TestsWorkspace { resetVector = 0x00000000l, relaxedPcCalculation = false ), -// new IBusSimplePlugin( -// interfaceKeepData = false, -// catchAccessFault = true -// ), - new IBusCachedPlugin( - config = InstructionCacheConfig( - cacheSize = 4096, - bytePerLine =32, - wayCount = 1, - wrappedMemAccess = true, - addressWidth = 32, - cpuDataWidth = 32, - memDataWidth = 32, - catchIllegalAccess = true, - catchAccessFault = true, - catchMemoryTranslationMiss = true, - asyncTagMemory = false, - twoStageLogic = true - ), - askMemoryTranslation = true, - memoryTranslatorPortConfig = MemoryTranslatorPortConfig( - portTlbSize = 4 - ) + new IBusSimplePlugin( + interfaceKeepData = false, + catchAccessFault = true ), -// new DBusSimplePlugin( -// catchAddressMisaligned = true, -// catchAccessFault = true, -// earlyInjection = false +// new IBusCachedPlugin( +// config = InstructionCacheConfig( +// cacheSize = 4096, +// bytePerLine =32, +// wayCount = 1, +// wrappedMemAccess = true, +// addressWidth = 32, +// cpuDataWidth = 32, +// memDataWidth = 32, +// catchIllegalAccess = true, +// catchAccessFault = true, +// catchMemoryTranslationMiss = true, +// asyncTagMemory = false, +// twoStageLogic = true +// ), +// askMemoryTranslation = true, +// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( +// portTlbSize = 4 +// ) // ), - new DBusCachedPlugin( - config = new DataCacheConfig( - cacheSize = 4096, - bytePerLine = 32, - wayCount = 1, - addressWidth = 32, - cpuDataWidth = 32, - memDataWidth = 32, - catchAccessError = true, - catchIllegal = true, - catchUnaligned = true, - catchMemoryTranslationMiss = true - ), -// memoryTranslatorPortConfig = null - memoryTranslatorPortConfig = MemoryTranslatorPortConfig( - portTlbSize = 6 - ) + new DBusSimplePlugin( + catchAddressMisaligned = true, + catchAccessFault = true, + earlyInjection = false ), +// new DBusCachedPlugin( +// config = new DataCacheConfig( +// cacheSize = 4096, +// bytePerLine = 32, +// wayCount = 1, +// addressWidth = 32, +// cpuDataWidth = 32, +// memDataWidth = 32, +// catchAccessError = true, +// catchIllegal = true, +// catchUnaligned = true, +// catchMemoryTranslationMiss = true +// ), +//// memoryTranslatorPortConfig = null +// memoryTranslatorPortConfig = MemoryTranslatorPortConfig( +// portTlbSize = 6 +// ) +// ), // new StaticMemoryTranslatorPlugin( // ioRange = _(31 downto 28) === 0xF // ), - new MemoryTranslatorPlugin( - tlbSize = 32, - virtualRange = _(31 downto 28) === 0xC, - ioRange = _(31 downto 28) === 0xF - ), +// new MemoryTranslatorPlugin( +// tlbSize = 32, +// virtualRange = _(31 downto 28) === 0xC, +// ioRange = _(31 downto 28) === 0xF +// ), new DecoderSimplePlugin( catchIllegalInstruction = true ), diff --git a/src/main/scala/vexriscv/demo/Murax.scala b/src/main/scala/vexriscv/demo/Murax.scala index 6b861d0..6635fb5 100644 --- a/src/main/scala/vexriscv/demo/Murax.scala +++ b/src/main/scala/vexriscv/demo/Murax.scala @@ -30,6 +30,7 @@ import vexriscv.{plugin, VexRiscvConfig, VexRiscv} case class MuraxConfig(coreFrequency : HertzNumber, onChipRamSize : BigInt, + onChipRamHexFile : String, bypassExecute : Boolean, bypassMemory: Boolean, bypassWriteBack: Boolean, @@ -44,6 +45,7 @@ object MuraxConfig{ def default = MuraxConfig( coreFrequency = 12 MHz, onChipRamSize = 8 kB, + onChipRamHexFile = null, bypassExecute = false, bypassMemory = false, bypassWriteBack = false, @@ -267,6 +269,40 @@ case class Murax(config : MuraxConfig) extends Component{ mask = bus.cmd.mask ) bus.cmd.ready := True + + if(onChipRamHexFile != null){ + def readHexFile(path : String, callback : (Int, Int) => Unit): Unit ={ + import scala.io.Source + def hToI(that : String, start : Int, size : Int) = Integer.parseInt(that.substring(start,start + size), 16) + + var offset = 0 + for (line <- Source.fromFile(path).getLines) { + if (line.charAt(0) == ':'){ + val byteCount = hToI(line, 1, 2) + val nextAddr = hToI(line, 3, 4) + offset + val key = hToI(line, 7, 2) + key match { + case 0 => + for(i <- 0 until byteCount){ + callback(nextAddr + i, hToI(line, 9 + i * 2, 2)) + } + case 2 => + offset = hToI(line, 9, 4) << 4 + case 4 => + offset = hToI(line, 9, 4) << 16 + case 3 => + case 1 => + } + } + } + } + + val initContent = Array.fill[BigInt](ram.wordCount)(0) + readHexFile(onChipRamHexFile,(address,data) => { + initContent(address >> 2) |= BigInt(data) << ((address & 3)*8) + }) + ram.initBigInt(initContent) + } } @@ -419,4 +455,12 @@ object Murax{ def main(args: Array[String]) { SpinalVerilog(Murax(MuraxConfig.default)) } +} + + +//Will blink led and echo UART RX to UART TX (in the verilator sim, type some text and press enter to send UART frame to the Murax RX pin) +object MuraxWithRamInit{ + def main(args: Array[String]) { + SpinalVerilog(Murax(MuraxConfig.default.copy(onChipRamSize = 4 kB, onChipRamHexFile = "src/main/ressource/hex/muraxDemo.hex"))) + } } \ No newline at end of file