From acb85a1fb88f6d3f94710e1306ccf2728888cf67 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Mon, 3 Apr 2017 01:33:54 +0200 Subject: [PATCH] Add some decoder comments --- .../Plugin/DecoderSimplePlugin.scala | 31 +++++-- .../SpinalRiscv/Plugin/ShiftPlugins.scala | 2 - src/main/scala/SpinalRiscv/TopLevel.scala | 84 ++++++++++--------- 3 files changed, 71 insertions(+), 46 deletions(-) diff --git a/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala b/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala index b189b24..8c1904e 100644 --- a/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala +++ b/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala @@ -11,8 +11,12 @@ import scala.collection.mutable.ArrayBuffer case class Masked(value : BigInt,care : BigInt){ var isPrime = true + def < (that: Masked) = value < that.value || value == that.value && ~care < ~that.care + def intersects(x: Masked) = ((value ^ x.value) & care & x.care) == 0 + def covers(x: Masked) = ((value ^ x.value) & care | (~x.care) & care) == 0 + def setPrime(value : Boolean) = { isPrime = value this @@ -173,22 +177,27 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean) extends Plugin[VexR object Symplify{ - val cache = mutable.HashMap[Bits,mutable.HashMap[Masked,Bool]](); + val cache = mutable.HashMap[Bits,mutable.HashMap[Masked,Bool]]() def getCache(addr : Bits) = cache.getOrElseUpdate(addr,mutable.HashMap[Masked,Bool]()) - def logicOf(addr : Bits,terms : Seq[Masked]) = terms.map(t => getCache(addr).getOrElseUpdate(t,t === addr)).asBits.orR + + //Generate terms logic for the given input + def logicOf(input : Bits,terms : Seq[Masked]) = terms.map(t => getCache(input).getOrElseUpdate(t,t === input)).asBits.orR - def apply(addr: Bits, mapping: Iterable[(Masked, Masked)],resultWidth : Int) : Bits = { - val addrWidth = widthOf(addr) + //Decode 'input' b using an mapping[key, decoding] specification + def apply(input: Bits, mapping: Iterable[(Masked, Masked)],resultWidth : Int) : Bits = { + val addrWidth = widthOf(input) (for(bitId <- 0 until resultWidth) yield{ val trueTerm = mapping.filter { case (k,t) => (t.care.testBit(bitId) && t.value.testBit(bitId))}.map(_._1) val falseTerm = mapping.filter { case (k,t) => (t.care.testBit(bitId) && !t.value.testBit(bitId))}.map(_._1) val symplifiedTerms = SymplifyBit.getPrimeImplicants(trueTerm.toSeq, falseTerm.toSeq, addrWidth) - logicOf(addr, symplifiedTerms) + logicOf(input, symplifiedTerms) }).asBits } } object SymplifyBit{ + + //Return a new term with only one bit difference with 'term' and not included in falseTerms. above => 0 to 1 dif, else 1 to 0 diff def genImplicitDontCare(falseTerms: Seq[Masked], term: Masked, bits: Int, above: Boolean): Masked = { for (i <- 0 until bits; if term.care.testBit(i)) { var t: Masked = null @@ -205,6 +214,7 @@ object SymplifyBit{ null } + //Return primes implicants for the trueTerms, falseTerms spec. Default value is don't care def getPrimeImplicants(trueTerms: Seq[Masked],falseTerms: Seq[Masked],inputWidth : Int): Seq[Masked] = { val primes = ArrayBuffer[Masked]() trueTerms.foreach(_.isPrime = true) @@ -233,9 +243,18 @@ object SymplifyBit{ for (p <- r; if p.isPrime) primes += p } + + verify(primes, trueTerms, falseTerms) primes } - + + //Verify that the 'terms' doesn't violate the trueTerms ++ falseTerms spec + def verify(terms : Seq[Masked], trueTerms : Seq[Masked], falseTerms : Seq[Masked]): Unit ={ + require(trueTerms.forall(trueTerm => terms.exists(_ covers trueTerm))) + require(falseTerms.forall(falseTerm => !terms.exists(_ covers falseTerm))) + } + + //Return primes implicants for the trueTerms, default value is False def getPrimeImplicants(trueTerms: Seq[Masked],inputWidth : Int): Seq[Masked] = { val primes = ArrayBuffer[Masked]() trueTerms.foreach(_.isPrime = true) diff --git a/src/main/scala/SpinalRiscv/Plugin/ShiftPlugins.scala b/src/main/scala/SpinalRiscv/Plugin/ShiftPlugins.scala index 1dfc292..2bfe95e 100644 --- a/src/main/scala/SpinalRiscv/Plugin/ShiftPlugins.scala +++ b/src/main/scala/SpinalRiscv/Plugin/ShiftPlugins.scala @@ -92,8 +92,6 @@ class LightShifterPlugin extends Plugin[VexRiscv]{ import pipeline.config._ import IntAluPlugin._ - - val immediateActions = List[(Stageable[_ <: BaseType],Any)]( SRC1_CTRL -> Src1CtrlEnum.RS, SRC2_CTRL -> Src2CtrlEnum.IMI, diff --git a/src/main/scala/SpinalRiscv/TopLevel.scala b/src/main/scala/SpinalRiscv/TopLevel.scala index 5cf348e..0e7bc3a 100644 --- a/src/main/scala/SpinalRiscv/TopLevel.scala +++ b/src/main/scala/SpinalRiscv/TopLevel.scala @@ -26,7 +26,7 @@ import spinal.lib._ object TopLevel { def main(args: Array[String]) { SpinalVerilog { - val config = VexRiscvConfig( + val configFull = VexRiscvConfig( pcWidth = 32 ) @@ -41,7 +41,7 @@ object TopLevel { // ) - val csrConfig = MachineCsrConfig( + val csrConfigAll = MachineCsrConfig( mvendorid = 11, marchid = 22, mimpid = 33, @@ -77,7 +77,7 @@ object TopLevel { // minstretAccess = CsrAccess.NONE // ) - config.plugins ++= List( + configFull.plugins ++= List( new PcManagerSimplePlugin(0x00000000l, false), new IBusSimplePlugin( interfaceKeepData = true, @@ -126,7 +126,7 @@ object TopLevel { // new HazardSimplePlugin(false, false, false, false), new MulPlugin, new DivPlugin, - new MachineCsr(csrConfig), + new MachineCsr(csrConfigAll), new BranchPlugin( earlyBranch = false, catchAddressMisaligned = true, @@ -134,41 +134,49 @@ object TopLevel { ) ) -// config.plugins ++= List( -// new PcManagerSimplePlugin(0x00000000l, false), -// new IBusSimplePlugin( -// interfaceKeepData = true -// ), -// new DecoderSimplePlugin( -// catchIllegalInstruction = false -// ), -// new RegFilePlugin( -// regFileReadyKind = Plugin.SYNC, -// zeroBoot = false -// ), -// new IntAluPlugin, -// new SrcPlugin, -//// new FullBarrielShifterPlugin, -// new LightShifterPlugin, -// new DBusSimplePlugin( -// catchUnalignedException = false -// ), -//// new HazardSimplePlugin(true, true, true, true), -// // new HazardSimplePlugin(false, true, false, true), -// new HazardSimplePlugin(false, false, false, false), -//// new MulPlugin, -//// new DivPlugin, -//// new MachineCsr(csrConfig), -// new BranchPlugin( -// earlyBranch = false, -// catchUnalignedException = false, -// prediction = NONE -// ) -// ) + val configLight = VexRiscvConfig( + pcWidth = 32 + ) - val toplevel = new VexRiscv(config) - toplevel.decode.input(config.INSTRUCTION).addAttribute("verilator public") - toplevel.decode.input(config.PC).addAttribute("verilator public") + configLight.plugins ++= List( + new PcManagerSimplePlugin(0x00000000l, false), + new IBusSimplePlugin( + interfaceKeepData = true, + catchAccessFault = false + ), + + new DBusSimplePlugin( + catchAddressMisaligned = false, + catchAccessFault = false + ), + new DecoderSimplePlugin( + catchIllegalInstruction = false + ), + new RegFilePlugin( + regFileReadyKind = Plugin.SYNC, + zeroBoot = false + ), + new IntAluPlugin, + new SrcPlugin, +// new FullBarrielShifterPlugin, + new LightShifterPlugin, +// new HazardSimplePlugin(true, true, true, true), + // new HazardSimplePlugin(false, true, false, true), + new HazardSimplePlugin(false, false, false, false), +// new MulPlugin, +// new DivPlugin, +// new MachineCsr(csrConfig), + new BranchPlugin( + earlyBranch = false, + catchAddressMisaligned = false, + prediction = NONE + ) + ) + + val toplevel = new VexRiscv(configFull) +// val toplevel = new VexRiscv(configLight) + toplevel.decode.input(toplevel.config.INSTRUCTION).addAttribute("verilator public") + toplevel.decode.input(toplevel.config.PC).addAttribute("verilator public") toplevel.decode.arbitration.isValid.addAttribute("verilator public") // toplevel.writeBack.input(config.PC).addAttribute("verilator public") // toplevel.service(classOf[DecoderSimplePlugin]).bench(toplevel)