From acf6ad3bfdfc8cd44f4432b055945fd1d7d38fe8 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Wed, 13 Sep 2023 14:55:35 +0200
Subject: [PATCH] Add doc about official RISC-V debug support

---
 README.md | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/README.md b/README.md
index c7578c6..28bace2 100644
--- a/README.md
+++ b/README.md
@@ -1294,6 +1294,42 @@ Write Address 0x04 ->
 
 The OpenOCD port is here: <https://github.com/SpinalHDL/openocd_riscv>
 
+#### EmbeddedRiscvJtag
+
+VexRiscv also support the official RISC-V debug specification (Thanks Efinix for the funding !).
+
+To enable it, you need to add the EmbeddedRiscvJtag to the plugin list : 
+
+```scala
+new EmbeddedRiscvJtag(
+  p = DebugTransportModuleParameter(
+    addressWidth = 7,
+    version      = 1,
+    idle         = 7
+  ),
+  withTunneling = false,
+  withTap = true
+)
+```
+
+And turn on the withPrivilegedDebug option in the CsrPlugin config.
+
+Here is an example of openocd tcl script to connect : 
+
+```tcl
+# ADD HERE YOUR JTAG ADAPTER SETTINGS
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10002FFF
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+
+init
+halt
+```
+
 #### YamlPlugin
 
 This plugin offers a service to other plugins to generate a useful Yaml file describing the CPU configuration. It contains, for instance, the sequence of instructions required