From adc37b269cc64f98293a7f7b0b20a947425b1cd3 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Thu, 11 Mar 2021 13:06:50 +0100 Subject: [PATCH] FpuPlugin.pending is now 6 bits --- src/main/scala/vexriscv/plugin/FpuPlugin.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/FpuPlugin.scala b/src/main/scala/vexriscv/plugin/FpuPlugin.scala index 6aa6831..498480d 100644 --- a/src/main/scala/vexriscv/plugin/FpuPlugin.scala +++ b/src/main/scala/vexriscv/plugin/FpuPlugin.scala @@ -241,7 +241,7 @@ class FpuPlugin(externalFpu : Boolean = false, val csr = pipeline plug new Area{ - val pendings = Reg(UInt(5 bits)) init(0) + val pendings = Reg(UInt(6 bits)) init(0) pendings := pendings + U(port.cmd.fire) - U(port.completion.fire) - U(port.rsp.fire) val hasPending = pendings =/= 0