diff --git a/src/test/cpp/raw/dcache/.gitignore b/src/test/cpp/raw/dcache/.gitignore new file mode 100644 index 0000000..c12cb2c --- /dev/null +++ b/src/test/cpp/raw/dcache/.gitignore @@ -0,0 +1,4 @@ +*.map +*.v +*.elf +*.o \ No newline at end of file diff --git a/src/test/cpp/raw/dcache/build/dcache.asm b/src/test/cpp/raw/dcache/build/dcache.asm new file mode 100644 index 0000000..698e5dc --- /dev/null +++ b/src/test/cpp/raw/dcache/build/dcache.asm @@ -0,0 +1,79 @@ + +build/dcache.elf: file format elf32-littleriscv + + +Disassembly of section .crt_section: + +80000000 <_start>: +80000000: 00000097 auipc ra,0x0 +80000004: 0b808093 addi ra,ra,184 # 800000b8 +80000008: 30509073 csrw mtvec,ra + +8000000c : +8000000c: 00100e13 li t3,1 +80000010: 00100093 li ra,1 +80000014: 00300113 li sp,3 +80000018: 00208093 addi ra,ra,2 +8000001c: 08209e63 bne ra,sp,800000b8 + +80000020 : +80000020: 00200e13 li t3,2 +80000024: f56700b7 lui ra,0xf5670 +80000028: 900ff137 lui sp,0x900ff +8000002c: 40000313 li t1,1024 + +80000030 : +80000030: 00100193 li gp,1 +80000034: 00200293 li t0,2 +80000038: 006303b3 add t2,t1,t1 +8000003c: 007181b3 add gp,gp,t2 +80000040: 007282b3 add t0,t0,t2 +80000044: 00312023 sw gp,0(sp) # 900ff000 +80000048: 0000a023 sw zero,0(ra) # f5670000 +8000004c: 00012203 lw tp,0(sp) +80000050: 06429463 bne t0,tp,800000b8 +80000054: fff30313 addi t1,t1,-1 +80000058: 00408093 addi ra,ra,4 +8000005c: 00410113 addi sp,sp,4 +80000060: 0000500f 0x500f +80000064: fc0316e3 bnez t1,80000030 + +80000068 : +80000068: 00300e13 li t3,3 +8000006c: f56700b7 lui ra,0xf5670 +80000070: 900ff137 lui sp,0x900ff +80000074: 40000313 li t1,1024 + +80000078 : +80000078: 00200193 li gp,2 +8000007c: 00300293 li t0,3 +80000080: 006303b3 add t2,t1,t1 +80000084: 007181b3 add gp,gp,t2 +80000088: 007282b3 add t0,t0,t2 +8000008c: 00012203 lw tp,0(sp) # 900ff000 +80000090: 00312023 sw gp,0(sp) +80000094: 0000a023 sw zero,0(ra) # f5670000 +80000098: 0000500f 0x500f +8000009c: 00012203 lw tp,0(sp) +800000a0: 00429c63 bne t0,tp,800000b8 +800000a4: fff30313 addi t1,t1,-1 +800000a8: 00408093 addi ra,ra,4 +800000ac: 00410113 addi sp,sp,4 +800000b0: fc0314e3 bnez t1,80000078 +800000b4: 0100006f j 800000c4 + +800000b8 : +800000b8: f0100137 lui sp,0xf0100 +800000bc: f2410113 addi sp,sp,-220 # f00fff24 +800000c0: 01c12023 sw t3,0(sp) + +800000c4 : +800000c4: f0100137 lui sp,0xf0100 +800000c8: f2010113 addi sp,sp,-224 # f00fff20 +800000cc: 00012023 sw zero,0(sp) +800000d0: 00000013 nop +800000d4: 00000013 nop +800000d8: 00000013 nop +800000dc: 00000013 nop +800000e0: 00000013 nop +800000e4: 00000013 nop diff --git a/src/test/cpp/raw/dcache/build/dcache.hex b/src/test/cpp/raw/dcache/build/dcache.hex new file mode 100644 index 0000000..6e9ef5d --- /dev/null +++ b/src/test/cpp/raw/dcache/build/dcache.hex @@ -0,0 +1,17 @@ +:0200000480007A +:10000000970000009380800B73905030130E100007 +:10001000930010001301300093802000639E20089D +:10002000130E2000B70067F537F10F90130300405F +:100030009301100093022000B3036300B3817100A9 +:10004000B38272002320310023A0000003220100AC +:10005000639442061303F3FF9380400013014100B1 +:100060000F500000E31603FC130E3000B70067F5D5 +:1000700037F10F90130300409301200093023000EA +:10008000B3036300B3817100B382720003220100E5 +:100090002320310023A000000F50000003220100A4 +:1000A000639C42001303F3FF93804000130141005F +:1000B000E31403FC6F000001370110F0130141F25B +:1000C0002320C101370110F0130101F223200100A8 +:1000D00013000000130000001300000013000000D4 +:0800E0001300000013000000F2 +:00000001FF diff --git a/src/test/cpp/raw/dcache/makefile b/src/test/cpp/raw/dcache/makefile new file mode 100644 index 0000000..5ebb942 --- /dev/null +++ b/src/test/cpp/raw/dcache/makefile @@ -0,0 +1,3 @@ +PROJ_NAME=dcache + +include ../common/asm.mk \ No newline at end of file diff --git a/src/test/cpp/raw/dcache/src/crt.S b/src/test/cpp/raw/dcache/src/crt.S new file mode 100644 index 0000000..8476c09 --- /dev/null +++ b/src/test/cpp/raw/dcache/src/crt.S @@ -0,0 +1,75 @@ +.globl _star +#define TEST_ID x28 + +_start: + la x1, fail + csrw mtvec, x1 + +test1: //Dummy test + li TEST_ID, 1 + li x1, 1 + li x2, 3 + addi x1, x1, 2 + bne x1, x2, fail + +test2: //No invalidate, without load => new one + li TEST_ID, 2 + li x1, 0xF5670000 + li x2, 0x900FF000 + li x6, 4096/4 +test2_repeat: + la x3, 1 + la x5, 2 + add x7, x6, x6 + add x3, x3, x7 + add x5, x5, x7 + sw x3, 0(x2) + sw x0, 0(x1) + lw x4, 0(x2) + bne x5,x4, fail + addi x6, x6, -1 + addi x1, x1, 4 + addi x2, x2, 4 +.word 0x000500F // dcache flush + bnez x6, test2_repeat + +test3: //with invalidate, with preload + li TEST_ID, 3 + li x1, 0xF5670000 + li x2, 0x900FF000 + li x6, 4096/4 +test3_repeat: + la x3, 2 + la x5, 3 + add x7, x6, x6 + add x3, x3, x7 + add x5, x5, x7 + lw x4, 0(x2) + sw x3, 0(x2) + sw x0, 0(x1) +.word 0x000500F // dcache flush + lw x4, 0(x2) + bne x5,x4, fail + addi x6, x6, -1 + addi x1, x1, 4 + addi x2, x2, 4 + bnez x6, test3_repeat + + + + j pass + +fail: + li x2, 0xF00FFF24 + sw TEST_ID, 0(x2) + +pass: + li x2, 0xF00FFF20 + sw x0, 0(x2) + + nop + nop + nop + nop + nop + nop diff --git a/src/test/cpp/raw/dcache/src/ld b/src/test/cpp/raw/dcache/src/ld new file mode 100644 index 0000000..93d8de8 --- /dev/null +++ b/src/test/cpp/raw/dcache/src/ld @@ -0,0 +1,16 @@ +OUTPUT_ARCH( "riscv" ) + +MEMORY { + onChipRam (W!RX)/*(RX)*/ : ORIGIN = 0x80000000, LENGTH = 128K +} + +SECTIONS +{ + + .crt_section : + { + . = ALIGN(4); + *crt.o(.text) + } > onChipRam + +} diff --git a/src/test/cpp/raw/icache/build/icache.asm b/src/test/cpp/raw/icache/build/icache.asm index edcd947..7521411 100644 --- a/src/test/cpp/raw/icache/build/icache.asm +++ b/src/test/cpp/raw/icache/build/icache.asm @@ -17,7 +17,7 @@ Disassembly of section .crt_section: 8000001c: 02209c63 bne ra,sp,80000054 80000020 : -80000020: 00100e13 li t3,1 +80000020: 00200e13 li t3,2 80000024: 01300093 li ra,19 80000028: 00000117 auipc sp,0x0 8000002c: 02410113 addi sp,sp,36 # 8000004c diff --git a/src/test/cpp/raw/icache/build/icache.hex b/src/test/cpp/raw/icache/build/icache.hex index ea4a88c..25eb34e 100644 --- a/src/test/cpp/raw/icache/build/icache.hex +++ b/src/test/cpp/raw/icache/build/icache.hex @@ -1,7 +1,7 @@ :0200000480007A :10000000970000009380400573905030130E10004D :10001000930010001301300093802000639C2002A5 -:10002000130E10009300300117010000130141026C +:10002000130E20009300300117010000130141025C :100030006F00000113000000130000001300000017 :10004000232011000F1000006F0040006F0080009F :100050006F000001370110F0130141F22320C101AC diff --git a/src/test/cpp/raw/icache/src/crt.S b/src/test/cpp/raw/icache/src/crt.S index 97b29b9..695c45b 100644 --- a/src/test/cpp/raw/icache/src/crt.S +++ b/src/test/cpp/raw/icache/src/crt.S @@ -13,7 +13,7 @@ test1: //Dummy test bne x1, x2, fail test2: - li TEST_ID, 1 + li TEST_ID, 2 li x1, 0x13 //nop la x2, test2_trigger j test2_aligned diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp index 665763c..5630ba6 100644 --- a/src/test/cpp/regression/main.cpp +++ b/src/test/cpp/regression/main.cpp @@ -1676,6 +1676,15 @@ public: case 0xF00FFF48u: mTimeCmp = (mTimeCmp & 0xFFFFFFFF00000000) | *data;break; case 0xF00FFF4Cu: mTimeCmp = (mTimeCmp & 0x00000000FFFFFFFF) | (((uint64_t)*data) << 32); break; } + if((addr & 0xFFFFF000) == 0xF5670000){ + uint32_t t = 0x900FF000 | (addr & 0xFFF); + uint32_t old = (*mem.get(t + 3) << 24) | (*mem.get(t + 2) << 16) | (*mem.get(t + 1) << 8) | (*mem.get(t + 0) << 0); + old++; + *mem.get(t + 0) = old & 0xFF; old >>= 8; + *mem.get(t + 1) = old & 0xFF; old >>= 8; + *mem.get(t + 2) = old & 0xFF; old >>= 8; + *mem.get(t + 3) = old & 0xFF; old >>= 8; + } }else{ switch(addr){ case 0xF00FFF10u: @@ -3562,6 +3571,9 @@ int main(int argc, char **argv, char **env) { #ifdef IBUS_CACHED redo(REDO,WorkspaceRegression("icache").withRiscvRef()->loadHex("../raw/icache/build/icache.hex")->bootAt(0x80000000u)->run(50e3);); #endif + #ifdef DBUS_CACHED + redo(REDO,WorkspaceRegression("dcache").loadHex("../raw/dcache/build/dcache.hex")->bootAt(0x80000000u)->run(500e3);); + #endif #ifdef MMU redo(REDO,WorkspaceRegression("mmu").withRiscvRef()->loadHex("../raw/mmu/build/mmu.hex")->bootAt(0x80000000u)->run(50e3););