From 49246e757f242b66e6b691fba28e022c15b94aa2 Mon Sep 17 00:00:00 2001 From: Leon Schuermann Date: Fri, 24 Feb 2023 16:34:06 -0500 Subject: [PATCH] CsrPlugin: insert FORMAL_HALT := False --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 8eeb898..b59fd89 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -670,6 +670,10 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep } } + // The CSR plugin will invoke a trap handler on exception, which does not + // count as halt-state by the RVFI spec, and neither do other instructions + // such as `wfi`, etc. Hence statically drive the output: + pipeline.stages.head.insert(FORMAL_HALT) := False case class Xtvec() extends Bundle { val mode = Bits(2 bits)