diff --git a/src/main/scala/vexriscv/Pipeline.scala b/src/main/scala/vexriscv/Pipeline.scala
index 2a04ef2..e9d93c2 100644
--- a/src/main/scala/vexriscv/Pipeline.scala
+++ b/src/main/scala/vexriscv/Pipeline.scala
@@ -14,7 +14,7 @@ trait Pipeline {
   val plugins = ArrayBuffer[Plugin[T]]()
   var stages = ArrayBuffer[Stage]()
   var unremovableStages = mutable.Set[Stage]()
-  val things = mutable.HashMap[PipelineThing[_], Any]()
+  val things = mutable.LinkedHashMap[PipelineThing[_], Any]()
 //  val services = ArrayBuffer[Any]()
 
   def stageBefore(stage : Stage) = stages(indexOf(stage)-1)
@@ -78,7 +78,7 @@ trait Pipeline {
       def setInsertStageId(stageId : Int) = insertStageId = stageId
     }
 
-    val inputOutputKeys = mutable.HashMap[Stageable[Data],KeyInfo]()
+    val inputOutputKeys = mutable.LinkedHashMap[Stageable[Data],KeyInfo]()
     val insertedStageable = mutable.Set[Stageable[Data]]()
     for(stageIndex <- 0 until stages.length; stage = stages(stageIndex)){
       stage.inserts.keysIterator.foreach(signal => inputOutputKeys.getOrElseUpdate(signal,new KeyInfo).setInsertStageId(stageIndex))
diff --git a/src/main/scala/vexriscv/Stage.scala b/src/main/scala/vexriscv/Stage.scala
index d86c256..5f3365a 100644
--- a/src/main/scala/vexriscv/Stage.scala
+++ b/src/main/scala/vexriscv/Stage.scala
@@ -61,15 +61,15 @@ class Stage() extends Area{
   }
 
 
-  val inputs   = mutable.HashMap[Stageable[Data],Data]()
-  val outputs  = mutable.HashMap[Stageable[Data],Data]()
-  val signals  = mutable.HashMap[Stageable[Data],Data]()
-  val inserts  = mutable.HashMap[Stageable[Data],Data]()
+  val inputs   = mutable.LinkedHashMap[Stageable[Data],Data]()
+  val outputs  = mutable.LinkedHashMap[Stageable[Data],Data]()
+  val signals  = mutable.LinkedHashMap[Stageable[Data],Data]()
+  val inserts  = mutable.LinkedHashMap[Stageable[Data],Data]()
 
-  val inputsDefault   = mutable.HashMap[Stageable[Data],Data]()
-  val outputsDefault  = mutable.HashMap[Stageable[Data],Data]()
+  val inputsDefault   = mutable.LinkedHashMap[Stageable[Data],Data]()
+  val outputsDefault  = mutable.LinkedHashMap[Stageable[Data],Data]()
 
-  val dontSample      = mutable.HashMap[Stageable[_], ArrayBuffer[Bool]]()
+  val dontSample      = mutable.LinkedHashMap[Stageable[_], ArrayBuffer[Bool]]()
 
   def dontSampleStageable(s : Stageable[_], cond : Bool): Unit ={
     dontSample.getOrElseUpdate(s, ArrayBuffer[Bool]()) += cond
diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index 0cdc896..fce4c15 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -550,7 +550,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
 
       val medeleg = supervisorGen generate new Area {
         val IAM, IAF, II, LAM, LAF, SAM, SAF, EU, ES, IPF, LPF, SPF = RegInit(False)
-        val mapping = mutable.HashMap(0 -> IAM, 1 -> IAF, 2 -> II, 4 -> LAM, 5 -> LAF, 6 -> SAM, 7 -> SAF, 8 -> EU, 9 -> ES, 12 -> IPF, 13 -> LPF, 15 -> SPF)
+        val mapping = mutable.LinkedHashMap(0 -> IAM, 1 -> IAF, 2 -> II, 4 -> LAM, 5 -> LAF, 6 -> SAM, 7 -> SAF, 8 -> EU, 9 -> ES, 12 -> IPF, 13 -> LPF, 15 -> SPF)
       }
       val mideleg = supervisorGen generate new Area {
         val ST, SE, SS = RegInit(False)
@@ -776,7 +776,7 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep
         val code = if(pipelinedInterrupt) Reg(UInt(trapCodeWidth bits)) else UInt(trapCodeWidth bits).assignDontCare()
         var privilegs = if (supervisorGen) List(1, 3) else List(3)
         val targetPrivilege = if(pipelinedInterrupt) Reg(UInt(2 bits)) else UInt(2 bits).assignDontCare()
-        val privilegeAllowInterrupts = mutable.HashMap[Int, Bool]()
+        val privilegeAllowInterrupts = mutable.LinkedHashMap[Int, Bool]()
         if (supervisorGen) privilegeAllowInterrupts += 1 -> ((sstatus.SIE && privilege === U"01") || privilege < U"01")
         privilegeAllowInterrupts += 3 -> (mstatus.MIE || privilege < U"11")
         while (privilegs.nonEmpty) {
diff --git a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
index e88a98c..e2ab111 100644
--- a/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DecoderSimplePlugin.scala
@@ -89,7 +89,7 @@ class DecoderSimplePlugin(catchIllegalInstruction : Boolean = false,
     import pipeline.config._
     import pipeline.decode._
 
-    val stageables = (encodings.flatMap(_._2.map(_._1)) ++ defaults.map(_._1)).toSet.toList
+    val stageables = (encodings.flatMap(_._2.map(_._1)) ++ defaults.map(_._1)).toList.distinct
 
     val stupidDecoder = false
     if(stupidDecoder){