diff --git a/src/main/scala/vexriscv/demo/Briey.scala b/src/main/scala/vexriscv/demo/Briey.scala
index 57872a9..2bf5947 100644
--- a/src/main/scala/vexriscv/demo/Briey.scala
+++ b/src/main/scala/vexriscv/demo/Briey.scala
@@ -13,8 +13,9 @@ import spinal.lib.com.uart.{Apb3UartCtrl, Uart, UartCtrlGenerics, UartCtrlMemory
 import spinal.lib.graphic.RgbConfig
 import spinal.lib.graphic.vga.{Axi4VgaCtrl, Axi4VgaCtrlGenerics, Vga}
 import spinal.lib.io.TriStateArray
+import spinal.lib.memory.sdram.SdramGeneration.SDR
 import spinal.lib.memory.sdram._
-import spinal.lib.memory.sdram.sdr.{Axi4SharedSdramCtrl, IS42x320D, SdramInterface, SdramLayout, SdramTimings}
+import spinal.lib.memory.sdram.sdr.{Axi4SharedSdramCtrl, IS42x320D, SdramInterface, SdramTimings}
 import spinal.lib.misc.HexTools
 import spinal.lib.soc.pinsec.{PinsecTimerCtrl, PinsecTimerCtrlExternal}
 import spinal.lib.system.debugger.{JtagAxi4SharedDebugger, JtagBridge, SystemDebugger, SystemDebuggerConfig}
@@ -413,6 +414,7 @@ object BrieyDe0Nano{
   def main(args: Array[String]) {
     object IS42x160G {
       def layout = SdramLayout(
+        generation = SDR,
         bankWidth   = 2,
         columnWidth = 9,
         rowWidth    = 13,