From f1d64eccc85b8fb0dc9c0302fe5bed6c0a76f3ad Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 3 Nov 2023 11:41:02 +0100 Subject: [PATCH 1/2] Fix demo --- .../scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala b/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala index 663f907..03b5deb 100644 --- a/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala +++ b/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala @@ -9,7 +9,7 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin} /** * This an example of VexRiscv configuration which can run the official RISC-V debug. * You can for instance : - * - generate this VexRiscv + * - sbt "runMain vexriscv.demo.GenFullWithOfficialRiscvDebug" * - cd src/test/cpp/regression * - make IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes SUPERVISOR=yes CSR=yes RVF=yes RVD=yes DEBUG_PLUGIN=RISCV WITH_RISCV_REF=no DEBUG_PLUGIN_EXTERNAL=yes DEBUG_PLUGIN=no VEXRISCV_JTAG=yes * @@ -122,9 +122,7 @@ object GenFullWithOfficialRiscvDebug extends App{ ) ) - def cpu() = new VexRiscv(config){ - println(config.getRegressionArgs().mkString(" ")) - } + def cpu() = new VexRiscv(config) SpinalVerilog(cpu()) } From e71b1be8a25fed1f0f792e018f331a2e3eef4dec Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Fri, 3 Nov 2023 11:43:59 +0100 Subject: [PATCH 2/2] demo fix --- .../scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala b/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala index 03b5deb..3e4e45a 100644 --- a/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala +++ b/src/main/scala/vexriscv/demo/GenFullWithOfficialRiscvDebug.scala @@ -11,7 +11,7 @@ import vexriscv.{VexRiscv, VexRiscvConfig, plugin} * You can for instance : * - sbt "runMain vexriscv.demo.GenFullWithOfficialRiscvDebug" * - cd src/test/cpp/regression - * - make IBUS=CACHED IBUS_DATA_WIDTH=64 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=64 DBUS_STORE_DATA_WIDTH=64 LRSC=yes AMO=yes DBUS_EXCLUSIVE=yes DBUS_INVALIDATE=yes MUL=yes DIV=yes SUPERVISOR=yes CSR=yes RVF=yes RVD=yes DEBUG_PLUGIN=RISCV WITH_RISCV_REF=no DEBUG_PLUGIN_EXTERNAL=yes DEBUG_PLUGIN=no VEXRISCV_JTAG=yes + * - make IBUS=CACHED IBUS_DATA_WIDTH=32 COMPRESSED=no DBUS=CACHED DBUS_LOAD_DATA_WIDTH=32 DBUS_STORE_DATA_WIDTH=32 MUL=yes DIV=yes SUPERVISOR=no CSR=yes DEBUG_PLUGIN=RISCV WITH_RISCV_REF=no DEBUG_PLUGIN_EXTERNAL=yes DEBUG_PLUGIN=no VEXRISCV_JTAG=yes * * This will run a simulation of the CPU which wait for a tcp-jtag connection from openocd. * That con connection can be done via openocd :