From b79b02152b735bbbd4fafd4ebd2cb126457d0248 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Thu, 18 Apr 2019 18:33:06 +0200 Subject: [PATCH] #60 Fix SFENCE_VMA deadlock --- src/main/scala/vexriscv/plugin/MmuPlugin.scala | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/MmuPlugin.scala b/src/main/scala/vexriscv/plugin/MmuPlugin.scala index a243484..f8a3418 100644 --- a/src/main/scala/vexriscv/plugin/MmuPlugin.scala +++ b/src/main/scala/vexriscv/plugin/MmuPlugin.scala @@ -253,10 +253,9 @@ class MmuPlugin(ioRange : UInt => Bool, } } - execute plug new Area{ - import execute._ - val tlbWriteBuffer = Reg(UInt(20 bits)) - when(arbitration.isFiring && input(IS_SFENCE_VMA)){ // || csrService.isWriting(CSR.SATP) + writeBack plug new Area{ + import writeBack._ + when(arbitration.isValid && input(IS_SFENCE_VMA)){ // || csrService.isWriting(CSR.SATP) for(port <- core.ports; line <- port.cache) line.valid := False //Assume that the instruction already fetched into the pipeline are ok } }