From b7f4f0981467eb542ce57ff4d5f323849e1d7abc Mon Sep 17 00:00:00 2001
From: Dolu1990 <papuchoud@hotmail.com>
Date: Tue, 21 Nov 2017 23:56:46 +0100
Subject: [PATCH] Update verilator makefiles to support the last SpinalHDL
 changes (process merges)

---
 src/main/scala/vexriscv/VexRiscv.scala         | 3 +++
 src/main/scala/vexriscv/plugin/CsrPlugin.scala | 2 +-
 src/test/cpp/briey/makefile                    | 2 +-
 src/test/cpp/murax/makefile                    | 2 +-
 src/test/cpp/regression/makefile               | 2 +-
 5 files changed, 7 insertions(+), 4 deletions(-)

diff --git a/src/main/scala/vexriscv/VexRiscv.scala b/src/main/scala/vexriscv/VexRiscv.scala
index 82f7a8c..178925e 100644
--- a/src/main/scala/vexriscv/VexRiscv.scala
+++ b/src/main/scala/vexriscv/VexRiscv.scala
@@ -62,6 +62,9 @@ class VexRiscv(val config : VexRiscvConfig) extends Component with Pipeline{
   writeBack.input(config.PC) keep() addAttribute(Verilator.public)
   writeBack.arbitration.isValid keep() addAttribute(Verilator.public)
   writeBack.arbitration.isFiring keep() addAttribute(Verilator.public)
+  decode.arbitration.removeIt.noBackendCombMerge //Verilator perf
+  memory.arbitration.removeIt.noBackendCombMerge
+  execute.arbitration.flushAll.noBackendCombMerge
 }
 
 
diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index 2d6d4e6..cbc5771 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -326,7 +326,7 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
 
       //Used to make the pipeline empty softly (for interrupts)
       val pipelineLiberator = new Area{
-        val enable = False
+        val enable = False.noBackendCombMerge //Verilator Perf
         prefetch.arbitration.haltByOther setWhen(enable)
         val done = ! List(fetch, decode, execute, memory).map(_.arbitration.isValid).orR
       }
diff --git a/src/test/cpp/briey/makefile b/src/test/cpp/briey/makefile
index 515373e..29d7d76 100644
--- a/src/test/cpp/briey/makefile
+++ b/src/test/cpp/briey/makefile
@@ -46,7 +46,7 @@ run: compile
 	./obj_dir/VBriey
 
 verilate:
-	verilator -cc  ../../../../Briey.v -CFLAGS -std=c++11  ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH --x-assign unique --exe main.cpp
+	verilator -cc  ../../../../Briey.v -CFLAGS -std=c++11  ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp
  	
 compile: verilate
 	make  -j  -C obj_dir/ -f VBriey.mk VBriey
diff --git a/src/test/cpp/murax/makefile b/src/test/cpp/murax/makefile
index a319cf5..83b5639 100644
--- a/src/test/cpp/murax/makefile
+++ b/src/test/cpp/murax/makefile
@@ -29,7 +29,7 @@ run: compile
 	./obj_dir/VMurax
 
 verilate:
-	verilator -cc  ../../../../Murax.v -CFLAGS -std=c++11  ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH --x-assign unique --exe main.cpp
+	verilator -cc  ../../../../Murax.v -CFLAGS -std=c++11  ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH -Wno-UNOPTFLAT --x-assign unique --exe main.cpp
  	
 compile: verilate
 	make  -j  -C obj_dir/ -f VMurax.mk VMurax
diff --git a/src/test/cpp/regression/makefile b/src/test/cpp/regression/makefile
index c62d8ba..3572e49 100644
--- a/src/test/cpp/regression/makefile
+++ b/src/test/cpp/regression/makefile
@@ -94,7 +94,7 @@ run: compile
 	./obj_dir/VVexRiscv
 
 verilate:
-	verilator -cc  ../../../../VexRiscv.v  -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread  ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-WIDTH --x-assign unique --exe main.cpp
+	verilator -cc  ../../../../VexRiscv.v  -O3 -CFLAGS -std=c++11 -LDFLAGS -pthread  ${ADDCFLAGS} --gdbbt ${VERILATOR_ARGS} -Wno-UNOPTFLAT -Wno-WIDTH --x-assign unique --exe main.cpp
  	
 compile: verilate
 	make  -j  -C obj_dir/ -f VVexRiscv.mk VVexRiscv