diff --git a/src/main/scala/vexriscv/ip/DataCache.scala b/src/main/scala/vexriscv/ip/DataCache.scala
index 02d3e9a..b3cf4dc 100644
--- a/src/main/scala/vexriscv/ip/DataCache.scala
+++ b/src/main/scala/vexriscv/ip/DataCache.scala
@@ -175,6 +175,7 @@ case class FenceFlags() extends Bundle {
 case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMasterSlave{
   val isValid = Bool()
   val isStuck = Bool()
+  val isFiring = Bool()
   val isUser = Bool()
   val haltIt = Bool()
   val isWrite = Bool()
@@ -187,7 +188,7 @@ case class DataCacheCpuWriteBack(p : DataCacheConfig) extends Bundle with IMaste
   val exclusiveOk = Bool()
 
   override def asMaster(): Unit = {
-    out(isValid,isStuck,isUser, address, fence, storeData)
+    out(isValid,isStuck,isUser, address, fence, storeData, isFiring)
     in(haltIt, data, mmuException, unalignedAccess, accessError, isWrite, keepMemRspData, exclusiveOk)
   }
 }
@@ -864,7 +865,7 @@ class DataCache(val p : DataCacheConfig, mmuParameter : MemoryTranslatorBusParam
 
     val lrSc = withInternalLrSc generate new Area{
       val reserved = RegInit(False)
-      when(io.cpu.writeBack.isValid && !io.cpu.writeBack.isStuck){
+      when(io.cpu.writeBack.isValid && io.cpu.writeBack.isFiring){
         reserved setWhen(request.isLrsc)
         reserved clearWhen(request.wr)
       }
diff --git a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
index 99786e7..3fb6498 100644
--- a/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusCachedPlugin.scala
@@ -395,6 +395,7 @@ class DBusCachedPlugin(val config : DataCacheConfig,
       import managementStage._
       cache.io.cpu.writeBack.isValid := arbitration.isValid && input(MEMORY_ENABLE)
       cache.io.cpu.writeBack.isStuck := arbitration.isStuck
+      cache.io.cpu.writeBack.isFiring := arbitration.isFiring
       cache.io.cpu.writeBack.isUser  := (if(privilegeService != null) privilegeService.isUser() else False)
       cache.io.cpu.writeBack.address := U(input(REGFILE_WRITE_DATA))
       cache.io.cpu.writeBack.storeData.subdivideIn(32 bits).foreach(_ := input(MEMORY_STORE_DATA_RF))
diff --git a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
index ac22dc4..d96d312 100644
--- a/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DBusSimplePlugin.scala
@@ -462,8 +462,9 @@ class DBusSimplePlugin(catchAddressMisaligned : Boolean = false,
       val atomic = withLrSc generate new Area{
         val reserved = RegInit(False)
         insert(ATOMIC_HIT) := reserved
-        when(arbitration.isFiring &&  input(MEMORY_ENABLE) && input(MEMORY_ATOMIC) && (if(mmuBus != null) !input(MMU_FAULT) else True) && !skipCmd){
-          reserved := !input(MEMORY_STORE)
+        when(arbitration.isFiring &&  input(MEMORY_ENABLE) && (if(mmuBus != null) !input(MMU_FAULT) else True) && !skipCmd){
+          reserved setWhen(input(MEMORY_ATOMIC))
+          reserved clearWhen(input(MEMORY_STORE))
         }
         when(input(MEMORY_STORE) && input(MEMORY_ATOMIC) && !input(ATOMIC_HIT)){
           skipCmd := True
diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
index 1b316e9..0178001 100644
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@@ -949,7 +949,7 @@ public:
 					if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
 					dWrite(pAddr, size, (uint8_t*)&i32_rs2);
 					pcWrite(pc + 4);
-				    lrscReserved = false;
+                    lrscReserved = false;
 				}
 			}break;
 			case 0x13: //ALUi
@@ -1111,6 +1111,7 @@ public:
 
                         lrscReserved = false;
 
+
                         uint32_t pAddr;
 						if(v2p(addr, &pAddr, READ_WRITE)){ trap(0, 15, addr); return; }
                         if(dRead(pAddr, 4, (uint8_t*)&readValue)){
@@ -1178,6 +1179,7 @@ public:
 					if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
 					dWrite(pAddr, 4, (uint8_t*)&i16_rf2);
                     pcWrite(pc + 2);
+                    lrscReserved = false;
 				}
 			}break;
 			case 8: rfWrite(rd32, regs[rd32] + i16_imm); pcWrite(pc + 2); break;
@@ -1243,6 +1245,7 @@ public:
 				} else {
 					if(v2p(address, &pAddr, WRITE)){ trap(0, 15, address); return; }
 					dWrite(pAddr, 4, (uint8_t*)&regs[iBits(2,5)]); pcWrite(pc + 2);
+                    lrscReserved = false;
 				}
 			}break;
 			}
@@ -2610,7 +2613,6 @@ public:
                         bool hit = reservationValid && reservationAddress == top->dBus_cmd_payload_address;
                         rsp.exclusive = hit;
                         cancel = !hit;
-                        reservationValid = false;
                     }
                     if(!cancel) {
                         for(int idx = 0;idx < 1;idx++){
@@ -2621,6 +2623,7 @@ public:
                         }
                     }
 
+                    reservationValid = false;
                     rsp.last = true;
                     rsp.error = error;
                     rsps.push(rsp);