diff --git a/src/main/scala/vexriscv/ip/InstructionCache.scala b/src/main/scala/vexriscv/ip/InstructionCache.scala
index 4df0f79..09b1a8a 100644
--- a/src/main/scala/vexriscv/ip/InstructionCache.scala
+++ b/src/main/scala/vexriscv/ip/InstructionCache.scala
@@ -251,7 +251,7 @@ case class InstructionCacheMemBus(p : InstructionCacheConfig) extends Bundle wit
 
   def toBmb() : Bmb = {
     val busParameter = p.getBmbParameter
-    val bus = Bmb(busParameter)
+    val bus = Bmb(busParameter).setCompositeName(this,"toBmb", true)
     bus.cmd.arbitrationFrom(cmd)
     bus.cmd.opcode := Bmb.Cmd.Opcode.READ
     bus.cmd.address := cmd.address.resized
diff --git a/src/main/scala/vexriscv/plugin/DebugPlugin.scala b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
index c04d167..34a878a 100644
--- a/src/main/scala/vexriscv/plugin/DebugPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/DebugPlugin.scala
@@ -96,7 +96,7 @@ case class DebugExtensionIo() extends Bundle with IMasterSlave{
 
 
 
-class DebugPlugin(val debugClockDomain : ClockDomain, hardwareBreakpointCount : Int = 0) extends Plugin[VexRiscv] {
+class DebugPlugin(var debugClockDomain : ClockDomain, hardwareBreakpointCount : Int = 0) extends Plugin[VexRiscv] {
 
   var io : DebugExtensionIo = null
   val injectionAsks = ArrayBuffer[(Stage, Bool)]()
diff --git a/src/test/cpp/raw/common/asm.mk b/src/test/cpp/raw/common/asm.mk
index 3d4b205..b63c80a 100644
--- a/src/test/cpp/raw/common/asm.mk
+++ b/src/test/cpp/raw/common/asm.mk
@@ -40,7 +40,7 @@ OBJS := $(addprefix $(OBJDIR)/,$(OBJS))
 
 
 
-all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm
+all: $(OBJDIR)/$(PROJ_NAME).elf $(OBJDIR)/$(PROJ_NAME).hex $(OBJDIR)/$(PROJ_NAME).asm $(OBJDIR)/$(PROJ_NAME).bin
 	@echo "done"
 
 $(OBJDIR)/%.elf: $(OBJS) | $(OBJDIR)
diff --git a/src/test/cpp/regression/main.cpp b/src/test/cpp/regression/main.cpp
index 6070183..67d7a0a 100644
--- a/src/test/cpp/regression/main.cpp
+++ b/src/test/cpp/regression/main.cpp
@@ -2350,6 +2350,7 @@ public:
 
 	bool reservationValid = false;
 	uint32_t reservationAddress;
+	uint32_t pendingSync = 0;
 
 	Workspace *ws;
 	VVexRiscv* top;
@@ -2363,11 +2364,17 @@ public:
 	virtual void onReset(){
 		top->dBus_cmd_ready = 1;
 		top->dBus_rsp_valid = 0;
+		top->dBus_inv_valid = 0;
+		top->dBus_ack_ready = 0;
+		top->dBus_sync_valid = 0;
 	}
 
 	virtual void preCycle(){
 		if (top->dBus_cmd_valid && top->dBus_cmd_ready) {
             if(top->dBus_cmd_payload_wr){
+                #ifdef DBUS_INVALIDATE
+                    pendingSync += 1;
+                #endif
                 #ifndef DBUS_EXCLUSIVE
                     bool error;
                     ws->dBusAccess(top->dBus_cmd_payload_address,1,2,top->dBus_cmd_payload_mask,&top->dBus_cmd_payload_data,&error);
@@ -2406,6 +2413,11 @@ public:
                 #endif
             }
 		}
+		#ifdef DBUS_INVALIDATE
+            if(top->dBus_sync_valid && top->dBus_sync_ready){
+                pendingSync -= 1;
+            }
+        #endif
 	}
 
 	virtual void postCycle(){
@@ -2446,6 +2458,10 @@ public:
                 }
             }
 		    top->dBus_ack_ready = (ws->dStall ? VL_RANDOM_I(7) < 100 : 1);
+		    if(top->dBus_sync_ready) top->dBus_sync_valid = 0;
+		    if(top->dBus_sync_valid == 0 && pendingSync != 0 && (ws->dStall ? VL_RANDOM_I(7) < 80 : 1) ){
+		        top->dBus_sync_valid = 1;
+            }
         #endif
 
 	}