From ba523c627a19bd54a42602d6d215d834edf3a763 Mon Sep 17 00:00:00 2001 From: Dolu1990 Date: Mon, 16 Nov 2020 12:37:48 +0100 Subject: [PATCH] Fix Csr ReadWrite interration with DBusCachedPlugin execute halt --- src/main/scala/vexriscv/plugin/CsrPlugin.scala | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala index 3c48033..7eee653 100644 --- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala +++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala @@ -1060,8 +1060,8 @@ class CsrPlugin(val config: CsrPluginConfig) extends Plugin[VexRiscv] with Excep val readData = Bits(32 bits) val writeInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_WRITE_OPCODE) val readInstruction = arbitration.isValid && input(IS_CSR) && input(CSR_READ_OPCODE) - val writeEnable = writeInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers - val readEnable = readInstruction && ! blockedBySideEffects && !arbitration.isStuckByOthers + val writeEnable = writeInstruction && !arbitration.isStuck + val readEnable = readInstruction && !arbitration.isStuck val readToWriteData = CombInit(readData) val writeData = if(noCsrAlu) writeSrc else input(INSTRUCTION)(13).mux(