From bb9261773b26513e3e983e6951500307b3f8fe62 Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Wed, 23 Oct 2019 00:02:08 +0200 Subject: [PATCH] Fix MulDiveIterative plugin when RSx have hazard in the execute stage --- src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala index a97a0ac..6820f8e 100644 --- a/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala +++ b/src/main/scala/vexriscv/plugin/MulDivIterativePlugin.scala @@ -80,7 +80,7 @@ class MulDivIterativePlugin(genMul : Boolean = true, //FrontendOK is only used for CPU configs without memory/writeback stages, were it is required to wait one extra cycle // to let's the frontend process rs1 rs2 registers - val frontendOk = if(flushStage != execute) True else RegInit(False) setWhen(arbitration.isValid && ((if(genDiv) input(IS_DIV) else False) || (if(genMul) input(IS_MUL) else False))) clearWhen(arbitration.isMoving) + val frontendOk = if(flushStage != execute) True else RegInit(False) setWhen(arbitration.isValid && !pipeline.service(classOf[HazardService]).hazardOnExecuteRS && ((if(genDiv) input(IS_DIV) else False) || (if(genMul) input(IS_MUL) else False))) clearWhen(arbitration.isMoving) val mul = ifGen(genMul) (if(customMul != null) customMul(rs1,rs2,memory,pipeline) else new Area{ assert(isPow2(mulUnrollFactor))