diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index bf65b19..897a206 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -1191,9 +1191,9 @@ class UserInterruptPlugin(interruptName : String, code : Int, privilege : Int =
     interrupt = in.Bool().setName(interruptName)
     val interruptPending =  RegNext(interrupt) init(False)
     val interruptEnable = RegInit(False).setName(interruptName + "_enable")
-    csr.addInterrupt(interruptPending , code, privilege, Nil)
+    csr.addInterrupt(interruptPending && interruptEnable, code, privilege, Nil)
     csr.r(csrAddress = CSR.MIP, bitOffset = code,interruptPending)
     csr.rw(csrAddress = CSR.MIE, bitOffset = code, interruptEnable)
   }
   override def build(pipeline: VexRiscv): Unit = {}
-}
\ No newline at end of file
+}