From bc90331c49a65f190926d3208b91349c800c25ec Mon Sep 17 00:00:00 2001 From: Charles Papon Date: Thu, 15 Jun 2017 13:54:34 +0200 Subject: [PATCH] Cleaning --- README.md | 6 +++--- src/main/scala/VexRiscv/demo/Briey.scala | 4 ---- 2 files changed, 3 insertions(+), 7 deletions(-) diff --git a/README.md b/README.md index 4ca3d96..7220952 100644 --- a/README.md +++ b/README.md @@ -25,13 +25,13 @@ You can find two example of CPU instantiation in : - src/main/scala/VexRiscv/GenFull.scala - src/main/scala/VexRiscv/GenSmallest.scala -To generate the corresponding RTL as a VexRiscv.v file, run : +To generate the corresponding RTL as a VexRiscv.v file, run (it could take time the first time you run it): ```sh -sbt run-main VexRiscv.GenFull +sbt "run-main VexRiscv.GenFull" # or -sbt run-main VexRiscv.GenSmallest +sbt "run-main VexRiscv.GenSmallest" ``` ## Tests diff --git a/src/main/scala/VexRiscv/demo/Briey.scala b/src/main/scala/VexRiscv/demo/Briey.scala index 25f659f..9686e2e 100644 --- a/src/main/scala/VexRiscv/demo/Briey.scala +++ b/src/main/scala/VexRiscv/demo/Briey.scala @@ -117,10 +117,6 @@ class Briey(config: BrieyConfig) extends Component{ reset = resetCtrl.vgaReset ) - val jtagClockDomain = ClockDomain( - clock = io.jtag.tck - ) - val axi = new ClockingArea(axiClockDomain) { val ram = Axi4SharedOnChipRam( dataWidth = 32,