From bd2787b562a66aa97b3e101cbcf91fc00dd2e73b Mon Sep 17 00:00:00 2001
From: Charles Papon <charles.papon.90@gmail.com>
Date: Fri, 1 Nov 2019 16:24:07 +0100
Subject: [PATCH] RegFilePlugin project X0 against boot glitches if no x0Init
 but zeroBoot

---
 src/main/scala/vexriscv/plugin/RegFilePlugin.scala | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala
index 2da66de..a34dc46 100644
--- a/src/main/scala/vexriscv/plugin/RegFilePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/RegFilePlugin.scala
@@ -96,6 +96,11 @@ class RegFilePlugin(regFileReadyKind : RegFileReadKind,
       regFileWrite.address := U(shadowPrefix(output(INSTRUCTION)(rdRange)))
       regFileWrite.data := output(REGFILE_WRITE_DATA)
 
+      //Ensure no boot glitches modify X0
+      if(!x0Init && zeroBoot) when(regFileWrite.address === 0){
+        regFileWrite.valid := False
+      }
+
       //CPU will initialise constant register zero in the first cycle
       if(x0Init) {
         val boot = RegNext(False) init (True)