From bd7c4c3281cbfd2fe0fe2c151ed35aa338e70db4 Mon Sep 17 00:00:00 2001
From: Craig Bishop <craig@craigjb.com>
Date: Mon, 26 Aug 2024 17:21:42 -0700
Subject: [PATCH] Add JTAG tunnel without TAP in EmbeddedRiscvJtag

---
 .../scala/vexriscv/plugin/EmbeddedRiscvJtag.scala    | 12 +++++++++++-
 1 file changed, 11 insertions(+), 1 deletion(-)

diff --git a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
index 8a1c668..1e625b2 100644
--- a/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
+++ b/src/main/scala/vexriscv/plugin/EmbeddedRiscvJtag.scala
@@ -14,6 +14,7 @@ import vexriscv._
 
 class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
                         var debugCd : ClockDomain = null,
+                        var jtagCd : ClockDomain = null,
                         var withTap : Boolean = true,
                         var withTunneling : Boolean = false
                         ) extends Plugin[VexRiscv] with VexRiscvRegressionArg{
@@ -61,7 +62,7 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
       dm.io.ctrl <> logic.io.bus
       logic.io.jtag <> jtag
     }
-    val dmiTunneled = if(withTap && withTunneling) new Area {
+    val dmiTunneledWithTap = if(withTap && withTunneling) new Area {
       val logic = DebugTransportModuleJtagTapWithTunnel(
         p.copy(addressWidth = 7),
         debugCd = ClockDomain.current
@@ -69,6 +70,15 @@ class EmbeddedRiscvJtag(var p : DebugTransportModuleParameter,
       dm.io.ctrl <> logic.io.bus
       logic.io.jtag <> jtag
     }
+    val dmiTunneledNoTap = if (!withTap && withTunneling) new Area {
+      val logic = DebugTransportModuleTunneled(
+        p.copy(addressWidth = 7),
+        debugCd = ClockDomain.current,
+        jtagCd = jtagCd
+      )
+      logic.io.instruction <> jtagInstruction
+      dm.io.ctrl <> logic.io.bus
+    }
 
     val privBus = pipeline.service(classOf[CsrPlugin]).debugBus.setAsDirectionLess()
     privBus <> dm.io.harts(0)