diff --git a/src/main/scala/vexriscv/plugin/BranchPlugin.scala b/src/main/scala/vexriscv/plugin/BranchPlugin.scala
index f6c0e39..4276b91 100644
--- a/src/main/scala/vexriscv/plugin/BranchPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/BranchPlugin.scala
@@ -147,8 +147,8 @@ class BranchPlugin(earlyBranch : Boolean,
     import pipeline._
     import pipeline.config._
 
-    val historyCache = Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) setName("branchCache")
-    val historyCacheWrite = historyCache.writePort
+    val historyCache = if(prediction == DYNAMIC) Mem(BranchPredictorLine(), 1 << historyRamSizeLog2) setName("branchCache") else null
+    val historyCacheWrite = if(prediction == DYNAMIC) historyCache.writePort else null
 
     //Read historyCache
     if(prediction == DYNAMIC) fetch plug new Area{
diff --git a/src/main/scala/vexriscv/plugin/CsrPlugin.scala b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
index 47996aa..57c4470 100644
--- a/src/main/scala/vexriscv/plugin/CsrPlugin.scala
+++ b/src/main/scala/vexriscv/plugin/CsrPlugin.scala
@@ -260,10 +260,10 @@ class CsrPlugin(config : CsrPluginConfig) extends Plugin[VexRiscv] with Exceptio
 
       //Define CSR registers
       val misa = new Area{
-        val base = Reg(UInt(2 bits)) init(U"01")
-        val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit)
+        val base = Reg(UInt(2 bits)) init(U"01") unsetRegIfNoAssignement
+        val extensions = Reg(Bits(26 bits)) init(misaExtensionsInit) unsetRegIfNoAssignement
       }
-      val mtvec = RegInit(U(mtvecInit,xlen bits))
+      val mtvec = RegInit(U(mtvecInit,xlen bits)) unsetRegIfNoAssignement
       val mepc = Reg(UInt(xlen bits))
       val mstatus = new Area{
         val MIE, MPIE = RegInit(False)