From c3c3a94c5db5cb516bd6376d220c75ce1777a2d4 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Wed, 13 Oct 2021 16:26:16 +0200
Subject: [PATCH] IBusSimplePlugin can now use a Vec based buffer

---
 src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala | 3 ++-
 src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala     | 5 +++--
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
index b247adf..54941d4 100644
--- a/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
+++ b/src/main/scala/vexriscv/demo/smp/VexRiscvSmpCluster.scala
@@ -266,7 +266,8 @@ object VexRiscvSmpClusterGen {
           prediction = NONE,
           catchAccessFault = false,
           compressedGen = rvc,
-          busLatencyMin = 2
+          busLatencyMin = 2,
+          vecRspBuffer = true
         ),
         if(withDataCache) new DBusCachedPlugin(
           dBusCmdMasterPipe = dBusCmdMasterPipe || dBusWidth == 32,
diff --git a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
index 5780ce8..1bb02bf 100644
--- a/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
+++ b/src/main/scala/vexriscv/plugin/IBusSimplePlugin.scala
@@ -236,7 +236,8 @@ class IBusSimplePlugin(    resetVector : BigInt,
                        val memoryTranslatorPortConfig : Any = null,
                            relaxPredictorAddress : Boolean = true,
                            predictionBuffer : Boolean = true,
-                           bigEndian : Boolean = false
+                           bigEndian : Boolean = false,
+                           vecRspBuffer : Boolean = false
                       ) extends IBusFetcherImpl(
     resetVector = resetVector,
     keepPcPlus4 = keepPcPlus4,
@@ -351,7 +352,7 @@ class IBusSimplePlugin(    resetVector : BigInt,
         //Manage flush for iBus transactions in flight
         val rspBuffer = new Area {
           val output = Stream(IBusSimpleRsp())
-          val c = StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0))
+          val c = new StreamFifoLowLatency(IBusSimpleRsp(), busLatencyMin + (if(cmdForkOnSecondStage && cmdForkPersistence) 1 else 0), useVec = vecRspBuffer)
           val discardCounter = Reg(UInt(log2Up(pendingMax + 1) bits)) init (0)
           discardCounter := discardCounter - (c.io.pop.valid && discardCounter =/= 0).asUInt
           when(iBusRsp.flush) {