diff --git a/src/main/scala/SpinalRiscv/Plugin/BranchPlugin.scala b/src/main/scala/SpinalRiscv/Plugin/BranchPlugin.scala
index 40a453e..24440c4 100644
--- a/src/main/scala/SpinalRiscv/Plugin/BranchPlugin.scala
+++ b/src/main/scala/SpinalRiscv/Plugin/BranchPlugin.scala
@@ -46,10 +46,12 @@ class BranchPlugin(earlyBranch : Boolean,prediction : BranchPrediction,historyRa
       REGFILE_WRITE_VALID -> True
     )
 
+    import IntAluPlugin._
+
     decoderService.addDefault(BRANCH_CTRL, BranchCtrlEnum.INC)
     decoderService.add(List(
-      JAL  -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JAL)),
-      JALR -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JALR, REG1_USE -> True)),
+      JAL  -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JAL , ALU_CTRL -> AluCtrlEnum.ADD_SUB)),
+      JALR -> (jActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.JALR, ALU_CTRL -> AluCtrlEnum.ADD_SUB, REG1_USE -> True)),
       BEQ  -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B)),
       BNE  -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B)),
       BLT  -> (bActions ++ List(BRANCH_CTRL -> BranchCtrlEnum.B, SRC_LESS_UNSIGNED -> False)),
diff --git a/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala b/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala
index 678bda5..f0dc2b8 100644
--- a/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala
+++ b/src/main/scala/SpinalRiscv/Plugin/DecoderSimplePlugin.scala
@@ -86,22 +86,23 @@ class DecoderSimplePlugin extends Plugin[VexRiscv] with DecoderService {
     val decodedBits = Bits(stageables.foldLeft(0)(_ + _.dataType.getBitsWidth) bits)
     val defaultBits = cloneOf(decodedBits)
 
-    assert(defaultValue == 0)
-    defaultBits := defaultValue
+//    assert(defaultValue == 0)
+//    defaultBits := defaultValue
+//
+//    val logicOr = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) &  key.care) === (key.value & key.care)), B(mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits))
+//    decodedBits := logicOr.foldLeft(defaultBits)(_ | _)
+
+
+    for(i <- decodedBits.range)
+      if(defaultCare.testBit(i))
+        defaultBits(i) := Bool(defaultValue.testBit(i))
+      else
+        defaultBits(i).assignDontCare()
+
 
     val logicOr = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) &  key.care) === (key.value & key.care)), B(mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits))
-    decodedBits := logicOr.foldLeft(defaultBits)(_ | _)
-
-
-    //    for(i <- decodedBits.range)
-    //      if(defaultCare.testBit(i))
-    //        defaultBits(i) := Bool(defaultValue.testBit(i))
-    //      else
-    //        defaultBits(i).assignDontCare()
-
-    //    val logicOr = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) &  key.care) === (key.value & key.care)), B(mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits))
-    //    val logicAnd = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) &  key.care) === (key.value & key.care)), B(~mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits))
-    //    decodedBits :=  (defaultBits | logicOr.foldLeft(B(0, decodedBits.getWidth bits))(_ | _)) & ~logicAnd.foldLeft(B(0, decodedBits.getWidth bits))(_ | _)
+    val logicAnd = for((key, mapping) <- spec) yield Mux[Bits](((input(INSTRUCTION) &  key.care) === (key.value & key.care)), B(~mapping.value & mapping.care, decodedBits.getWidth bits) , B(0, decodedBits.getWidth bits))
+    decodedBits :=  (defaultBits | logicOr.foldLeft(B(0, decodedBits.getWidth bits))(_ | _)) & ~logicAnd.foldLeft(B(0, decodedBits.getWidth bits))(_ | _)
 
 
     //Unpack decodedBits and insert fields in the pipeline
diff --git a/src/main/scala/SpinalRiscv/TopLevel.scala b/src/main/scala/SpinalRiscv/TopLevel.scala
index 0193c4c..33b72cc 100644
--- a/src/main/scala/SpinalRiscv/TopLevel.scala
+++ b/src/main/scala/SpinalRiscv/TopLevel.scala
@@ -40,12 +40,12 @@ object TopLevel {
         new FullBarrielShifterPlugin,
 //        new LightShifterPlugin,
         new DBusSimplePlugin,
-//        new HazardSimplePlugin(false, true, false, true),
-        new HazardSimplePlugin(true, true, true, true),
+        new HazardSimplePlugin(false, true, false, true),
+//        new HazardSimplePlugin(true, true, true, true),
 //        new HazardSimplePlugin(false, false, false, false),
         new MulPlugin,
         new DivPlugin,
-        new BranchPlugin(false, DYNAMIC)
+        new BranchPlugin(false, NONE)
       )
 
       val toplevel = new VexRiscv(config)
diff --git a/src/test/cpp/testA/main.cpp b/src/test/cpp/testA/main.cpp
index 64cdc80..e64ace7 100644
--- a/src/test/cpp/testA/main.cpp
+++ b/src/test/cpp/testA/main.cpp
@@ -490,6 +490,8 @@ long timer_end(struct timespec start_time){
     return diffInNanos;
 }
 
+#define redo(count,that) for(uint32_t xxx = 0;xxx < count;xxx++) that
+
 int main(int argc, char **argv, char **env) {
 	Verilated::randReset(2);
 	Verilated::commandArgs(argc, argv);
@@ -500,16 +502,16 @@ int main(int argc, char **argv, char **env) {
 		#ifndef  REF
 		TestA().run();
 		for(const string &name : riscvTestMain){
-			RiscvTest(name).run();
+			redo(5,RiscvTest(name).run();)
 		}
 		for(const string &name : riscvTestMemory){
-			RiscvTest(name).run();
+			redo(5,RiscvTest(name).run();)
 		}
 		for(const string &name : riscvTestMul){
-			RiscvTest(name).run();
+			redo(5,RiscvTest(name).run();)
 		}
 		for(const string &name : riscvTestDiv){
-			RiscvTest(name).run();
+			redo(5,RiscvTest(name).run();)
 		}
 		#endif
 		Dhrystone("dhrystoneO3",true,true).run(1e6);