From c57da3c7dc71872251dae877c4fe5de7739d0366 Mon Sep 17 00:00:00 2001
From: Dolu1990 <charles.papon.90@gmail.com>
Date: Sun, 19 Feb 2023 09:50:41 +0100
Subject: [PATCH] fix too early

---
 README.md | 36 ------------------------------------
 1 file changed, 36 deletions(-)

diff --git a/README.md b/README.md
index 28bace2..c7578c6 100644
--- a/README.md
+++ b/README.md
@@ -1294,42 +1294,6 @@ Write Address 0x04 ->
 
 The OpenOCD port is here: <https://github.com/SpinalHDL/openocd_riscv>
 
-#### EmbeddedRiscvJtag
-
-VexRiscv also support the official RISC-V debug specification (Thanks Efinix for the funding !).
-
-To enable it, you need to add the EmbeddedRiscvJtag to the plugin list : 
-
-```scala
-new EmbeddedRiscvJtag(
-  p = DebugTransportModuleParameter(
-    addressWidth = 7,
-    version      = 1,
-    idle         = 7
-  ),
-  withTunneling = false,
-  withTap = true
-)
-```
-
-And turn on the withPrivilegedDebug option in the CsrPlugin config.
-
-Here is an example of openocd tcl script to connect : 
-
-```tcl
-# ADD HERE YOUR JTAG ADAPTER SETTINGS
-
-set _CHIPNAME riscv
-jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x10002FFF
-
-set _TARGETNAME $_CHIPNAME.cpu
-
-target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
-
-init
-halt
-```
-
 #### YamlPlugin
 
 This plugin offers a service to other plugins to generate a useful Yaml file describing the CPU configuration. It contains, for instance, the sequence of instructions required